MAX1329 Datasheet, PDF (48/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
ADC LT Alarm Register
The ADC LT Alarm register contains the less-than
mode, trip count, and threshold settings. Writing the
register address resets the trip counters to zero. The LT
alarm is functional for the normal, fast power-down, and
burst modes.
LTAM: ADC Less-Than Alarm Mode bit (default = 0).
LTAM = 0 means that the alarm trips need not be con-
secutive to cause the LTA Status bit to be set. LTAM = 1
means that the alarm trips must be consecutive before
the LTA Status bit is set.
LTAC<2:0>: ADC Less-Than Alarm Trip Count bits
(default = 000). LTAC<2:0> set the number of conver-
sion results needed to be less than the alarm threshold
before the LTA Status bit is set.
LTAT<11:0>: ADC Less-Than Alarm Threshold bits
(default = 0x000). When the required number of ADC
conversions results less than the threshold set by the
LTAT<11:0> bits have been completed, the LTA Status
bit is set in the Status register. Clearing the LTA Status
bit by reading the Status register or writing to the ADC LT
Alarm register restarts the trip count. The LTAT<11:0>
bits are in binary format when the ADC is in unipolar
mode and two’s complement format when the ADC is in
bipolar mode. Disable the LT alarm by setting
LTAT<11:0> to 0x000 when the ADC is in unipolar mode
and 0x800 when the ADC is in bipolar mode.
NAME
DEFAULT
MSB
LTAM
0
NAME
DEFAULT
LTAT7
0
LTAC2
0
LTAT6
0
LTAC1
0
LTAT5
0
LTAC0
0
LTAT11
0
LTAT10
0
LTAT9
0
LTAT4
0
LTAT3
0
LTAT2
0
LTAT1
0
LTAT8
0
LSB
LTAT0
0
Table 13b. ADC Less-Than Alarm Trip
Count Bit Configuration
LTAC2
0
0
0
0
1
1
1
1
LTAC1
0
0
1
1
0
0
1
1
LTAC0
0
1
0
1
0
1
0
1
NUMBER OF TRIPS
1
2
3
4
5
6
7
8
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