MAX1329 Datasheet, PDF (52/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
FIFO Sequence Register
A write to the FIFO Sequence register steps DACA to the
next FIFOA word. A valid write consists of the 8-bit
address and 8 bits of data, where the data bits are don’t-
care bits. The FIFO location increments on the 16th rising
edge of SCLK. Successive writes sequence the entire
contents of the FIFOA Data register to the DACA output
register. The FIFO can also be sequenced with the
DPIOs configured as DLDA or DLAB. The FIFO
Sequence register is a write-only register.
Clock Control Register
The Clock Control register enables the internal oscilla-
tor and the CLKIO output, sets the ADC acquisition
time, and controls the CLKIO, ADC, and charge-pump
programmable dividers.
ODLY: Oscillator Turn-Off Delay bit (default = 0). Set
ODLY = 0 to allow the oscillator to turn off immediately
when powered down by the OSCE bit. If ODLY = 1, the
oscillator turns off 1024 CLKIO clock cycles after it is
powered down by the OSCE bit. ODLY also affects
DPIO sleep mode (SLPB). When ODLY = 1, OSCE = 1,
and CLKIO<1:0> does not equal 00b, SLPB is delayed
by 1024 CLKIO clocks.
OSCE: Internal Oscillator Enable bit (default = 1). Set
OSCE = 1 to enable the internal 3.6864MHz oscillator.
Set OSCE = 0 to disable the internal oscillator and
apply an external oscillator at CLKIO. When turning off,
CLKIO drives low before becoming an input. Do not
leave CLKIO unconnected when configured as an
input. The APIOs and DPIOs can be configured as a
wake-up to set the OSCE bit.
CLKIO<1:0>: CLKIO Configuration bits (default = 10).
CLKIO<1:0> control the CLKIO input and output divider
settings. See Table 18 for the CLKIO configurations.
Changes to the CLKIO<1:0> bits occur on the falling
edge of CLKIO. The ODLY bit is ignored and has no
effect when the CLKIO is disabled. When OSCE = 1,
changing the CLKIO output frequency does not change
the frequency of the clock to the ADC and charge-
pump clock dividers. When OSCE = 0, the output of the
CLKIO input dividers is applied to the ADC and charge-
pump clock dividers. The changes can take up to four
CLKIO clock cycles due to internal synchronization.
ADDIV<1:0>: ADC Clock Divider bits (default = 00).
ADDIV<1:0> configures the ADC clock divider (see
Table 19), and the output is the ADC master clock
(Figure 3). If OSCE = 1, the input to the ADC clock
divider is the output of the 3.6864MHz oscillator. If
OSCE = 0 and CLKIO<1:0> ≠ 00, the output of the
CLKIO input divider is applied to the input of the ADC
clock divider.
ACQCK<1:0> ADC Acquisition Clock bits (default =
01). ACQCK<1:0> set the number of ADC master
clocks used for the ADC acquisition (see Table 20). For
gains of 1 or 2 (GAIN<1:0> = 0X in the ADC Control
register), the number of acquisition clocks can be set
for 2, 4, 8, or 16. For gains of 4 or 8 (GAIN<1:0> = 1X),
the number of acquisition clocks can be programmed
to be 4, 8, 16, or 32.
NAME
DEFAULT
MSB
ODLY
0
OSCE
1
CLKIO1
1
CLKIO0
0
ADDIV1
0
ADDIV0
0
ACQCK1
0
LSB
ACQCK0
1
Table 18. CLKIO Bit Configuration
CLKIO1 CLKIO0
0
0
0
1
1
0
1
1
CLKIO INPUT
MODE
(OSCE = 0)
Input
f_CLKIO/4
f_CLKIO/2
f_CLKIO
CLKIO OUTPUT
MODE (MHz)
(OSCE = 1)
Disabled
(output low)
1.2288
2.4567
4.9152
Table 19. ADC Clock Divider Bit
Configuration
ADDIV1
0
0
1
1
ADDIV0
0
1
0
1
ADC CLOCK DIVIDER
Divide by 1
Divide by 2
Divide by 4
Divide by 8
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