MAX1329 Datasheet, PDF (10/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS
(DV_DD = 1.8V to 3.6V, AV_DD = 2.7V to 5.5V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SERIAL-INTERFACE TIMING PARAMETERS (DV_DD = 2.7V to 3.6V) (Figures 1 and 2)
SCLK Operating Frequency
f_OP
0
SCLK Cycle Time
t_CYC
50
DIN to SCLK Setup
t_DS
15
DIN to SCLK Hold
t_DH
0
SCLK Fall to Output Data Valid
t_DO
CS Fall to Output Enable
t_DV
CS Rise to Output Disable
t_TR
CS to SCLK Rise Setup
t_CSS
15
CS to SCLK Rise Hold
t_CSH
0
SCLK Pulse-Width High
t_CH
20
SCLK Pulse-Width Low
t_CL
20
20
MHz
ns
ns
ns
20
ns
24
ns
24
ns
ns
ns
ns
ns
SERIAL-INTERFACE TIMING PARAMETERS (DV_DD = 1.8V to 3.6V) (Figures 1 and 2)
SCLK Operating Frequency
f_OP
0
SCLK Cycle Time
t_CYC
100
DIN to SCLK Setup
t_DS
30
DIN to SCLK Hold
t_DH
0
SCLK Fall to Output Data Valid
t_DO
CS Fall to Output Enable
t_DV
CS Rise to Output Disable
t_TR
CS to SCLK Rise Setup
t_CSS
30
CS to SCLK Rise Hold
t_CSH
0
SCLK Pulse-Width High
t_CH
40
SCLK Pulse-Width Low
t_CL
40
10
MHz
ns
ns
ns
40
ns
48
ns
48
ns
ns
ns
ns
ns
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DV_DD = 2.7V to 3.6V, C_L = 20pF)
SPI Write to DPIO Output Valid
t_SD
From last SCLK rising edge
50
ns
DPIO Rise/Fall Input to Interrupt
Asserted Delay
t_DI
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
55
ns
DPIO Input to Analog Block Delay
t_DA
When controlling ADC, DACs, or switches
40
ns
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DV_DD = 1.8V to 3.6V, C_L = 20pF)
SPI Write to DPIO Output Valid
t_SD
From last SCLK rising edge
100
ns
DPIO Rise/Fall Input to Interrupt
Asserted Delay
t_DI
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
150
ns
DPIO Input to Analog Block Delay
t_DA
When controlling ADC, DACs, or switches
50
ns
ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1–APIO4, DV_DD = 2.7V to 3.6V, AV_DD = 2.7V to 5.5V, C_L = 20pF)
SPI Write to APIO Output Valid
t_SD
From last SCLK rising edge
50
ns
APIO Rise/Fall Input to Interrupt
Asserted Delay
t_DI
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
50
ns
CS to APIO4 Propagation Delay
t_{DCA AP4MD<1:0> = 11}
35
ns
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