MAX1329 Datasheet, PDF (44/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
ADC Data Register
The ADC Data register contains the result from the most
recently completed analog-to-digital conversion. The
12-bit result is stored in the ADCDATA<11:0> bits. The
data format is binary for unipolar mode and two’s com-
plement for bipolar mode. The ADC Data register con-
tents are the same as the ADC FIFO contents at the last
written address, unless writes to the ADC FIFO have
been inhibited.
MSB
NAME ADCDATA11 ADCDATA10
DEFAULT
0
0
ADCDATA9
0
ADCDATA8
0
ADCDATA7
0
ADCDATA6
0
ADCDATA5
0
ADCDATA4
0
LSB
NAME
ADCDATA3 ADCDATA2 ADCDATA1 ADCDATA0
X
X
X
X
DEFAULT
0
0
0
0
X
X
X
X
X = Don’t care.
ADC FIFO Register
The ADC FIFO register contents are different for write
and read modes. In write mode, the ADC FIFO register
sets the working depth of the FIFO and the address that
generates an interrupt. In read mode, the ADC FIFO
register holds the ADC FIFO data and FIFO address.
Write Format
A serial interface write to the ADC FIFO register moves
the FIFO write and read pointers to address 0.
AFFD<3:0>: ADC FIFO Depth bits (default = 0000).
AFFD<3:0> sets the working depth of the FIFO (see
Table 10). If set to a depth of zero, the ADC FIFO is dis-
abled and writes to the AFF (ADC FIFO Full) bit in the
Status register are also disabled. AFFD<3:0> are write-
only bits.
AFFI<3:0>: ADC FIFO Interrupt Address bits (default =
0000). AFFI<3:0> sets the FIFO address. After each
successful ADC conversion, the conversion results are
transferred from the ADC Data register to the FIFO
location indicated by the FIFO write pointer, and the
FIFO write pointer is incremented. When the FIFO write
pointer exceeds the value in AFFI<3:0>, the AFF bit in
the Status register (Table 11) is asserted. Set the
AFFI<3:0> value equal to or less than the AFFD<3:0>
value. If set to a value greater than AFFD<3:0>,
AFFI<3:0> is forced to the AFFD<3:0> value. If
AFFD<3:0> is set to 0000 (depth of zero), the ADC
FIFO is disabled and writes to the AFF bit are also dis-
abled. AFFI<3:0> are write-only bits.
NAME
DEFAULT
MSB
AFFD3
0
AFFD2
0
AFFD1
0
AFFD0
0
AFFI3
0
AFFI2
0
AFFI1
0
LSB
AFFI0
0
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