MAX1329 Datasheet, PDF (32/78 Pages) Maxim Integrated Products – 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
Table 2. Direct-Mode Definitions
COMMAND NAME
ADC Convert
DACA Write
DACB Write
Register Mode*
*See Table 3.
START
1
0
0
0
CONTROL
MUX<3:0>
1 R/W 0
1 R/W 1
GAIN<1:0>
BIP
DACA<11:0>
DACB<11:0>
0 R/W ADDRESS (ADR<4:0>)
DATA (D<255:0>, D<23:0>, D<15:0>, or
D<7:0>)
Asserting the BIPA bit with SYMA = 1 creates phases
three and four (see Figure 9g). Phases three and four
repeat the same sequence as in phases one and two,
respectively, but the FIFO data is subtracted from the
input register data this time through. The final value in
phase two is not repeated before proceeding with
phase three. The resulting waveform is composed of all
four phases.
Asserting the BIPA bit with SYMA = 0 creates phase
four (see Figure 9e). Phase four repeats the same
sequence as in phase one in reverse order, but the
FIFO data is subtracted from the input register data. In
this case, the last location in the FIFO is repeated
before sequencing back to the beginning.
When the CONA bit is not asserted, the output is static
once the end of the programmed pattern has been
reached. Asserting the CONA bit causes the patterns
described above to repeat without repeating the final
value (see Figures 9b, 9d, 9f, and 9h).
The FIFO Enable bit (FFEA) enables the ability to create
waveforms. The FFEA must be disabled to write to the
FIFOA Data register. Any change in the FIFOA Control
register reinitializes the FIFO sequencing logic and the
next sequence loads the input register value. The
DACA Input and/or Output registers can be written
directly and not affect the sequencing logic. Writing to
the DACA input register effectively moves the DC offset
of the waveform on the next sequence and writing to
the DACA output register immediately changes the out-
put level independent of the FIFO.
Serial Interface
The MAX1329/MAX1330 feature a 4-wire serial interface
consisting of a chip select (CS), serial clock (SCLK),
data in (DIN), and data out (DOUT). CS must be low to
allow data to be clocked into or out of the shift register.
DOUT is high-impedance while CS is high, unless
APIO1 is programmed for SPI mode. The data is
clocked in at DIN into the shift register on the rising
edge of SCLK. Data is clocked out at DOUT on the
falling edge of SCLK. The serial interface is compatible
with SPI modes CPOL = 0, CPHA = 0 and CPOL = 1,
CPHA = 1. A write operation takes effect on the rising
edge of SCLK used to shift in the LSB (or last bit of the
data word being written). If CS goes high before the
complete transfer, the write is ignored. CS must be
forced high between commands.
Direct-Mode Commands
The direct-mode commands include the ADC Convert
command and DACA and DACB Read and Write com-
mands. The ADC Convert command is an 8-bit com-
mand that initiates an ADC conversion, selects the
conversion channel through the multiplexer, sets the
PGA gain, and selects bipolar or unipolar mode. If an
ADC Convert command is issued during a conversion
in progress, the current conversion aborts and a new
one begins. The MUX<3:0>, GAIN<1:0>, and BIP bits
settings in the ADC Setup register are overwritten by
the values in the ADC Convert command.
The DACA and DACB Data Write commands set the
DACA and DACB input and/or output register values,
respectively. The DACA and DACB data write modes
are determined by the DAC Control register. The DACA
and DACB data read commands read the DACA and
DACB input register data, respectively.
In register mode, an address byte identifies each regis-
ter. The data registers are 8, 16, or 24 bits wide. The
ADC and DACA FIFO Data registers are variable length
up to 256 bits wide. Figures 10–17 provide example
timing diagrams for various commands.
ADC Conversion Timing
Configure the ADC Control and Setup registers before
attempting any conversions. Initiate an ADC conver-
sion with the 8-bit ADC Convert command (see Table
2) or by toggling a DPIO input configured for an ADC
conversion-start function. When a conversion com-
pletes, the result is ready to be read in the data regis-
ter. In burst mode, the ADC data is delivered real time
on DOUT.
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