IS66WVC2M16ALL Datasheet, PDF (7/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Functional Description
In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular
in low-power, portable applications.
The 32Mb device contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by
16 bits. This device implements the same high-speed bus interface found on burst mode Flash
products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization
process. Initialization will configure the BCR and the RCR with their default settings (see Table 3
and Table 8). VDD and VDDQ must be applied simultaneously.
When they reach a stable level at or above 1.7V, the device will require 150μs to complete
its self-initialization process. During the initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD=1.7V
VDD
VDDQ
tPU > 150us
Device Initialization
Device ready for
normal operation
Rev.A | June 2011
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