IS66WVC2M16ALL Datasheet, PDF (31/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
AC Characteristics
Table15 . Asynchronous READ Cycle Timing Requirements
Symbol
Parameter
t_AA
t_AADV
t_APA
t_AVH
t_AVS
t_BA
t_BHZ
t_BLZ
t_CEM
t_CEW
t_CO
t_CVS
t_HZ
t_LZ
t_OE
t_OH
t_OHZ
t_OLZ
t_PC
t_RC
t_VP
Address Acess Time
ADV# Access Time
Page Access Time
Address hold from ADV# HIGH
Address setup to ADV# HIGH
UB#, LB# Access Time
UB#, LB# Disable to High-Z Output
UB#, LB# Enable to Low-Z Output
Maximum CE# pulse width
CE# low to WAIT Valid
Chip Select Access Time
CE# low to ADV# HIGH
Chip Disable to DQ and WAIT High-Z Output
Chip enable to Low-Z output
OE# low to Valid Output
Output hold from address change
Output disable to DQ High-Z output
Output enable to Low-Z output
Page READ cycle time
READ cycle time
ADV# Low pulse width
70ns
Min
Max
70
70
20
2
5
70
8
10
4
1
7.5
70
7
8
10
20
5
8
3
20
70
5
Unit Notes
ns
ns
ns
ns
ns
ns
ns
1
ns
2
us
3
ns
ns
ns
ns
1
ns
2
ns
ns
ns
1
ns
2
ns
ns
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 17. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 17. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or
VOL.
3. Page mode enable only
Rev.A | June 2011
www.issi.com – [e-mail]
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