IS66WVC2M16ALL Datasheet, PDF (24/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to
adjust for different data bus loading scenarios. The reduced-strength options are intended
for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory
bus. The reduced-drive-strength option minimizes the noise generated on the data bus
during READ operations. Full output drive strength should be selected when using a
discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are
configured at half-drive strength during testing. See Table 5 for additional information.
Table 5. Drive Strength
BCR[5]
0
BCR[4]
0
Drive Strength
Full
0
1
1/2(Default)
1
0
1/4
1
1
Impedance Typ (Ω)
25 ~ 30
50
100
Reserved
Use Recommendation
CL = 30pF to 50pF
CL = 15pF to 30pF
104MHz at light load
CL = 15pF or lower
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the de-asserted or asserted state
respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data
bus going valid or invalid (see Figure 13).
Figure 13. WAIT Configuration During Burst Operation
CLK
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
WAIT
BCR[8]=0
Data valid/invalid in current cycle
WAIT
Notes :
Non-default BCR setting : WAIT active LOW
BCR[8]=1
Data valid/invalid in next cycle
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
Rev.A | June 2011
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