IS66WVC2M16ALL Datasheet, PDF (25/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Latency codes from two
(three clocks) to six (seven clocks) are supported (see Tables 6 and 7, Figure 14, and
Figure 15).
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency
counter. However, WAIT must be monitored to detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refresh collisions. The latency counter must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst begins after the number of clock cycles configured by the
latency counter. (See Table 7 and Figure 15)
Table 6. Variable Latency Configuration Codes (BCR[14] = 0)
BCR
[13:11]
Latency
Configuration
Code
Latency
Refresh
Normal
Collision
Max Input CLK Frequency (MHz)
-96
-12
010 2 (3 clocks)
2
4
66 (15.0ns)
52 (18.5ns)
011 3 (4 clocks)-default
3
100 4 (5 clocks)
4
6
104 (9.62ns)
80 (12.5ns)
8
others Reserved
-
-
-
-
Notes:
1. Latency is the number of clock cycles from the initialization of a burst operation until data appears.
Data is transferred on the next clock cycle.
Figure 14. Latency Counter (Variable Latency, No Refresh Collision)
A[20:0]
CLK
VALID
ADDRESS
ADV#
DQ0-
DQ15
DQ0-
DQ15
DQ0-
DQ15
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
Code 2 (3 clocks)
Code 3 (4 clocks) : Default
VALID
OUTPUT
Code 4 (5 clocks)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Rev.A | June 2011
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