IS66WVC2M16ALL Datasheet, PDF (52/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Figure 37: Burst WRITE at End-of-Row (Wrap Off)
t_CLK
CLK
Address
ADV# VIH
UB#/LB#
WE#
OE# ^VIH
WAIT
t_KHTL
t_HZ
t_HZ
VIH
CE#
VIL
DQ0-
DQ15
VALID
INPUT
VALID
INPUT
NOTE2
t_HZ
VALID
INPUT
End of Row (A[7:0]=FFh)
Notes:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT
active LOW; WAIT asserted during delay.
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins
(before the second CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after
WAIT asserts with BCR[8] = 1).
Rev.A | June 2011
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