IS66WVC2M16ALL Datasheet, PDF (33/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Table17 . Asynchronous WRITE Cycle Timing Requirements
Symbol
Parameter
t_AS
Address and ADV# LOW Setup Time
t_AVH
Address hold from ADV# HIGH
t_AVS
Address setup to ADV# HIGH
t_AW
Address Valid to End of Write
t_BW
UB#, LB# Select to End of Write
t_CEW
CE# low to WAIT Valid
t_CPH
CE# HIGH between Subsequent
Asynchronous cycles
t_CVS
CE# low to ADV# HIGH
t_CW
Chip Enable to End of Write
t_DH
Data Hold from Write Time
t_DW
Data Write Setup Time
t_HZ
Chip Disable to DQ and WAIT High-Z Output
t_LZ
Chip enable to Low-Z output
t_OW
End WRITE to Low-Z output
t_VP
ADV# Low pulse width
t_VS
ADV# Setup to End of Write
t_WC
WRITE cycle time
t_WHZ
WRITE to DQ High-Z Output
t_WP
WRITE Pulse Width
t_WPH
WRITE pulse width HIGH
t_WR
WRITE Recovery Time
70ns
Unit
Notes
Min
Max
0
ns
2
ns
5
ns
70
ns
70
ns
1
7.5
ns
5
ns
7
ns
70
ns
0
ns
20
ns
8
ns
1
10
ns
2
5
ns
2
5
ns
70
ns
70
ns
8
ns
1
45
ns
3
10
ns
0
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 17. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 17.
The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. WE# must be limited to t_CEM (4us)
Rev.A | June 2011
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