IS66WVC2M16ALL Datasheet, PDF (56/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Figure 41: Burst WRITE interrupted by Burst READ – Variable Latency Mode
CLK
Address
DQ0-
DQ15
ADV#
CE#
VALID
ADDRESS
t_SP t_HD
t_SP t_HD
t_CSP
WRITE burst interrupted with new READ
VALID
ADDRESS
VALID
INPUT
t_ACLK t_KOH
VALID VALID VALID VALID
OUTPUT OUTPUT OUTPUT OUTPUT
t_CEM (Note 3)
UB#/LB#
WE#
t_SP t_HD
OE#
WAIT
t_CEW
HiZ
t_KHTL
t_OLZ
t_BOE
t_OHZ
t_HZ
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst READ in variable latency mode:
fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
Rev.A | June 2011
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