IS66WVC2M16ALL Datasheet, PDF (22/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Table 3 describes the control bits in the BCR. At power-up, the BCR is set to 1D1Fh.
The BCR is accessed using CRE and A[19:18] = 10b, or through the configuration
register software sequence with DQ[15:0] = 0001h on the third cycle.
Table 3. Bus configuration Register
Bit Number
Definition
Remark
20
19 – 18
17 – 16
Reserved
Register Select
Reserved
Must be set to “0”
00 = Select RCR
01 = Select DIDR
10 = Select BCR
Must be set to “0”
15
14
13 – 11
10
9
8
7–6
5–4
3
2–0
Operating mode
Initial Latency
Latency Count
WAIT Polarity
Reserved
WAIT Configuration
Reserved
Output Impedance
Burst mode
Burst Length
0 = Synchronous burst access mode
1 = Asynchronous access mode (default)
0 = Variable (default)
1 = Fixed
000 = 9 clock cycles
001 = reserved
010 = 3 clock cycles
011 = 4 clock cycles (default)
100 = 5 clock cycles
101 = 6 clock cycles
110 = 7 clock cycles
111 = reserved
0 = Active LOW : Data valid at WAIT HIGH
1 = Active HIGH : Data valid at WAIT LOW (default)
Must be set to “0”
0 = Asserted during delay
1 = Asserted one data cycle before delay (default)
Must be set to “0”
00 = Full drive
01 = ½ Drive (default)
10 = ¼ Drive
11 = Reserved
0 = Burst wrap within the burst length
1 = Burst no wrap (default)
001 = 4 words
010 = 8 words
011 = 16 words
100 = 32 words
111 = continuous (default)
Others = Reserved
Notes :
1.Burst wrap and length apply to both READ and WRITE operations.
Rev.A | June 2011
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