IS66WVC2M16ALL Datasheet, PDF (11/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Asynchronous Mode
Asynchronous mode uses industry-standard SRAM control signals (CE#, OE#, WE#, UB#,
and LB#). READ operations (Figure 4) are initiated by bringing CE#, OE#, UB#/LB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed.
WRITE operations (Figure 5) occur when CE#, WE#, UB#/LB# are driven LOW. During
asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override
OE#. The data to be written is latched on the rising edge of CE#, WE#, UB#/LB#
(whichever occurs first). Asynchronous operations (page mode disabled) can either
use the ADV input to latch the address, or ADV can be driven LOW during the entire
READ/WRITE operations
During asynchronous operation, the CLK input must be held LOW. WAIT will be driven
during asynchronous READs, and its state should be ignored. WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing (ADV# LOW)
Address
t_RC = READ cycle Time
VALID
ADDRESS
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
Notes:
1. ADV must remain LOW for PAGE MODE operation.
VALID
OUTPUT
Rev.A | June 2011
www.issi.com – [e-mail]
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