IS66WVC2M16ALL Datasheet, PDF (10/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Burst Write Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a WRITE (WE# =LOW, Figure 3).
Data is placed to the data bus (DQ0~DQ15) with consecutive clock cycles when WAIT de-asserts.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of a row, unless wrapping within the burst length.
A full 4 word synchronous write access is shown in Figure 3 and the AC characteristics are specified in
Table 18.
Figure 3. Synchronous Write Access Timing
t_CLK
CLK
Address
DQ0-
DQ15
ADV#
CE#
VALID
ADDRESS
t_SP
t_HD
t_AS
t_AS
t_CSP
UB#/LB#
t_SP
t_HD
DATA IN
DATA IN
DATA IN
DATA IN
t_CEM
t_SP t_HD
t_HD
t_CBPH
t_HD
WE#
t_SP
t_HD
t_CEW
WAIT ^HiZ
t_KHTL
Write Burst Identified (WE#=LOW)
Rev.A | June 2011
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