IS66WVC2M16ALL Datasheet, PDF (13/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
preformed, then adjacent addresses can be read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM
page. Any change in addresses A[4] or higher will initiate a new tAA access time.
Figure 6 shows the timing for a page mode access. Page mode takes advantage of the fact
that adjacent addresses can be read in a shorter period of time than random addresses.
WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW. CE# must
be driven HIGH upon completion of a page mode access. WAIT will be driven while the device
is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH.
ADV must be driven LOW during all page mode READ accesses.
Due to refresh considerations, CE# must not be LOW longer than tCEM.
Figure 6. Page Mode READ Operation (ADV# LOW)
Address
DQ0-
DQ15
ADD0
t_AA
ADD1
ADD2
ADD3
t_APA
t_APA
t_APA
D0
D1
D2
D3
CE#
UB#/LB#
OE#
WE#
Notes:
1. ADV must remain LOW for PAGE MODE operation.
Rev.A | June 2011
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