IS66WVC2M16ALL Datasheet, PDF (57/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC2M16ALL
Figure 42: Burst WRITE interrupted by Burst WRITE – Variable Latency Mode
CLK
Address
DQ0-
DQ15
ADV#
CE#
VALID
ADDRESS
t_SP t_HD
t_SP t_HD
t_CSP
WRITE burst interrupted with new WRITE
VALID
ADDRESS
VALID
INPUT
VALID VALID VALID
INPUT INPUT INPUT
VALID
INPUT
t_HD
t_CEM (Note 3)
UB#/LB#
WE#
t_SP t_HD
OE#
t_CEW
WAIT
t_KHTL
Notes:
1. Non-default BCR settings for burst WRITE interrupted by WRITE: fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown
for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after the first data received by the controller).
Rev.A | June 2011
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