X3100-01 Datasheet, PDF (8/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Power-up Timing (Initial Power-up or after
Sleep Mode)
T_PUR
VCC
V_SLR
0V
V_RGO
0V
VOLTAGE REGULATOR OUTPUT STATUS
(INTERNAL SIGNAL) VRGS
OVERCURRENT DETECTION STATUS
(INTERNAL SIGNAL) _OCDS
STATUS REGISTER BIT 0
VRGS+OCDS
STATUS REGISTER BIT 2
(SWCEN = 0) CCES+OVDS
STATUS REGISTER BIT 2
(SWCEN = 1)
OVDS
5V ±10% (STABLE AND REPEATABLE)
V_RGO TUNED TO 5V ±0.5%
5V
2ms (Typ.)
1
0
T_OC
1
1 = X3100/1 in Overcurrent Protection Mode
0 = X3100/1 NOT in Overcurrent Protection Mode
0
1 _{1 = X3100/1 in Overcurrent Protection Mode OR VRGO Not Yet Tuned}
0 = X3100/1 NOT in Overcurrent Protection Mode AND VRGO Tuned
0
T_OV+200ms
1
0
1 = V_CELL < V_CE OR X3100/1 in Overcharge Protection Mode
0 = V_CELL > V_CE OR X3100/1 NOT in Overcharge Protection Mode
1
0
1 = X3100/1 in Overcharge Protection Mode
0 = X3100/1 NOT in Overcharge Protection Mode
AS2_AS0
SPI PORT
T_OV + 200ms OR T_UV + 200ms (WHICHEVER IS LONGER)
Any Read or Write Operation, except
turn-on of FETs can start here.
Charge, Discharge FETs can be
turned on here.
8
FN8110.1
January 3, 2008