X3100-01 Datasheet, PDF (4/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Pin Descriptions (Continued)
PIN
NUMBER PIN NAME
BRIEF DESCRIPTION
23
OVP/ Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the
LMON present mode of operation of the X3100 or X3101.
Over-charge Voltage Protection (OVP)
This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is
possible when OVP/LMON=V_SS, and cell charge is prohibited when OVP/LMO = V_CC. In this configuration the X3100 and
X3101 turn off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to
the application of charging voltage for an extended period of time (see section “Over-charge Protection” on page 14).
Load Monitor (LMON)
In Over-current Protection mode, a small test current (7.5µA typ.) is passed out of this pin to sense the load resistance. The
measured load resistance determines whether or not the X3100 or X3101 returns from an over-current protection mode (see
section “Over-Current Protection” on page 19).
24
UVP/ Over-discharge protection output/Over-current protection output. Pin UVP/OCP controls the battery cell discharge via
OCP an external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when
UVP/OCP=Vcc. The X3100 and X3101 turn the external power FET off when the X3100 or X3101 detects either:
Over-discharge Protection (UVP)
In this case, pin 24 is referred to as “Over-discharge (Under-Voltage) protection (UVP)” (see section “Over-discharge
Protection” on page 16). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to
excessively low voltages.
Over-current protection (OCP)
In this case, pin 24 is referred to as “Over-current protection (OCP)” (see section “Over-Current Protection” on page 19).
UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of
a surge current resulting from a stalled disk drive).
25
RGO Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage
at this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage
for the device.
26
RGC Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on.
27
RGP Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an
external current limit resistor and provides a current limit voltage.
28
VCC Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up
circuits.
principles of operation
The X3100 and X3101 provide two distinct levels of
functionality and battery cell protection:
First, in Normal mode, the device periodically checks each
cell for an overcharge and overdischarge state, while
continuously watching for a pack over-current condition. A
protection mode violation results from an over-charge, over-
discharge, or overcurrent state. The thresholds for these
states are selected by the user through software. When one
of these conditions occur, a Discharge FET or a Charge FET
or both FETs are turned off to protect the battery pack. In an
over-discharge condition, the X3100 and X3101 devices go
into a low power sleep mode to conserve battery power.
During sleep, the voltage regulator turns off, removing power
from the microcontroller to further reduce pack current.
Second, in Monitor mode, a microcontroller with A/D converter
measures battery cell voltage and pack current via pin AO and
the X3100 or X3101 on-board MUX. The user can thus
implement protection, charge/discharge, cell balancing or gas
gauge software algorithms to suit the specific application and
characteristics of the cells used. While monitoring these
voltages, all protection circuits are on continuously.
In a typical application, the microcontroller is also
programmed to provide an SMBus interface along with the
Smart Battery System interface protocols. These additions
allow an X3100 or X3101 based module to adhere to the
latest industry battery pack standards.
Typical Application Circuit
The X3100 and X3101 have been designed to operate
correctly when used as connected in the Typical Application
Circuit (see Figure 1 on page 5).
The power MOSFET’s Q1 and Q2 are referred to as the
“Discharge FET” and “Charge FET,” respectively. Since
these FETs are p-channel devices, they will be ON when the
gates are at V_SS, and OFF when the gates are at V_CC. As
their names imply, the discharge FET is used to control cell
discharge, while the charge FET is used to control cell
charge. Diode D₁ allows the battery cells to receive charge
even if the Discharge FET is OFF, while diode D₂ allows the
cells to discharge even if the charge FET is OFF. D₁ and D₂
are integral to the Power FETs. It should be noted that the
cells can neither charge nor discharge if both the charge FET
and discharge FET are OFF.
4
FN8110.1
January 3, 2008