X3100-01 Datasheet, PDF (22/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
The internal gain of the X3100 or X3101 current sense
voltage amplifier can be selected by using the WCNTR
Instruction to set bits CSG1 and CSG0 in the control
register (Table 14). The CSG1 and CSG0 bits select
one of four input resistors to Op Amp OP1. The feed-
back resistors remain constant. This ratio of input to
feedback resistors determines the gain. Putting exter-
nal resistors in series with the inputs reduces the gain of
the amplifier.
VCS1 and VCS2 are read at AO with respect to a DC
bias voltage of 2.5V. Therefore, the voltage range of
VCS₁₂ and VCS₂₁ changes depending upon the direc-
tion of current flow (i.e. battery cells are in Charge or
Discharge—Table 21).
Table 26. AO Voltage Range for VCS₁₂ and VCS₂₁
AO
Cell State
AO Voltage Range
VCS₁₂
VCS₁₂
VCS₂₁
VCS₂₁
Charge
Discharge
Charge
Discharge
2.5V ≤ AO ≤ 5.0V
0V ≤ AO ≤ 2.5V
0V ≤ AO ≤ 2.5V
2.5V ≤ AO ≤ 5.0V
By calculating the difference of VCS₁₂ and VCS₂₁ the
offset voltage of the internal op-amp circuitry is can-
celled. This allows for the accurate calculation of cur-
rent flow into and out of the battery cells.
Pack current is calculated using the following formula:
Pack Current = -----------------------------⁽--V-----C-----S----¹---²----^–-----V----C-----S----²---¹----⁾----------------------------
(2)(gain setting)(current sense resistor)
VOLTAGE REGULATOR
The X3100 and X3101 are able to supply peripheral
devices with a regulated 5VDC±0.5% output at pin
RGO. The voltage regulator should be configured
externally as shown in Figure 8.
The non-inverting input of OP1 is fed with a high preci-
sion 5VDC supply. The voltage at the output of the
voltage regulator (V_RGO) is compared to this 5V refer-
ence via the inverting input of OP1. The output of OP1
in turn drives the regulator pnp transistor (Q1). The
negative feedback at the regulator output maintains
the voltage at 5VDC±0.5% (including ripple) despite
changes in load, and differences in regulator transistors.
When power is applied to pin VCC of the X3100 or
X3101, V_RGO is regulated to 5VDC±10% for a nominal
time of T_OC+2ms. During this time period, V_RGO is
“tuned” to attain a final value of 5VDC±0.5% (Figure ).
The maximum current that can flow from the voltage
regulator (I_LMT) is controlled by the current limiting
resistor (R_LMT) connected between RGP and VCC.
When the voltage across VCC and RGP reaches a
nominal 2.5V (i.e. the threshold voltage for the FET), Q2
switches ON, shorting VCC to the base of Q1. Since
the base voltage of Q1 is now higher than the emitter
voltage, Q1 switches OFF, and hence the supply current
goes to zero.
Typical values for R_LMT and I_LMT are shown in Table
27. In order to protect the voltage regulator circuitry
from damage in case of a short-circuit, R_LMT ≥ 10Ω
should always be used.
Table 27. Typical Values for R_LMT and I_LMT
R_LMT
10Ω
Voltage Regulator Current Limit (I_LMT)
250mA ± 50% (Typical)
25Ω
100mA ± 50% (Typical)
50Ω
50mA ± 50% (Typical)
When choosing the value of R_LMT, the drive limitations
of the PNP transistor used should also be taken into
consideration. The transistor should have a gain of at
least 100 to support an output current of 250mA.
Figure 8. Voltage Regulator Operation
To Internal Voltage
Regulating Circuitry
VCC
X3100/X3101
Tuning
Q2
RGP
5VDC
Precision
Voltage
Reference
+
_
OP1
RGC
RGO
Un-Regulated
Voltage
Input
R_LMT
I_LMT
Q1
Regulated
5VDC Output
0.1 ^VRGO
µF
4KBIT EEPROM MEMORY
The X3100 and X3101 contain a CMOS 4k-bit serial
EEPROM, internally organized as 512 x 8 bits. This
memory is accessible via the SPI port, and features
the IDLock function.
22
FN8110.1
January 3, 2008