X3100-01 Datasheet, PDF (24/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Table 30. X3100/X3101 Instruction Set
Instruction
Name
Instruction
Format*
Description
WREN
0000 0110 Set the write enable latch (write enable operation)—Figure 9
WRDI
0000 0100 Reset the write enable latch (write disable operation)—Figure 9
EEWRITE
0000 0010 Write command followed by address/data (4kbit EEPROM)—Figure 10, Figure 11
EEREAD STAT 0000 0101 Reads IDLock settings & status of EEPROM EEWRITE instruction—Figure 12
EEREAD
0000 0011 Read operation followed by address (for 4kbit EEPROM)—Figure 13
WCFIG
0000 1001 Write to configuration register followed by two bytes of data—Figure 2, Figure 14.
Data stored in SRAM only and will power-up to previous settings—Figure 1
WCNTR
0000 1010 Write to control register, followed by two bytes of data—Figure 15
RDSTAT
0000 1011 Read contents of status register—Figure 16
SET IDL
0000 0001 Set EEPROM ID lock partition followed by partition byte—Figure 17
*Instructions have the MSB in leftmost position and are transferred MSB first.
Write Enable/Write Disable (WREN/WRDI)
Any write to a nonvolatile array or register, requires
the WREN command be sent prior to the write com-
mand. This command sets an internal latch allowing
the write operation to proceed. The WRDI command
resets the internal latch if the system decides to abort
a write operation. See Figure 9.
Figure 9. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence
CS
SCK
SI
01234567
Instruction
(1 Byte)
High Impedance
SO
WREN
WRDI
24
FN8110.1
January 3, 2008