X3100-01 Datasheet, PDF (27/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
EEPROM Read Sequence (EEREAD)
When reading from the X3100 or X3101 EEPROM
memory, CS is first pulled LOW to select the device.
The 8-bit EEREAD instruction is transmitted to the
X3100 or X3101, followed by the 16-bit address, of
which the last 9 bits are used (bits [15:9] specified to be
zeroes). After the EEREAD opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially
by continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (01FFh), the address counter rolls
over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by taking CS HIGH. Refer to the EEPROM Read
(EEREAD) operation sequence illustrated in Figure 13.
Figure 13. EEPROM (EEREAD) Read Operation Sequence
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30 31
EEREAD Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
3210
Data Out
High Impedance
SO
76543210
27
FN8110.1
January 3, 2008