X3100-01 Datasheet, PDF (18/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued)
Event
[3]
(3,4)
[4]
(4,5)
[5]
Event Description
Return from sleep mode (but still in over-discharge protection mode):
— Vcc rises above the “Return from Sleep mode threshold Voltage” (V_SLR)—This would normally occur in the
case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and
not the battery pack cells.
— Power is returned to ALL internal circuitry
— 5VDC output is returned to the regulator output (RGO).
— Access is enabled to the X3100/X3101 via the SPI port.
— The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control
register, although it will have no effect at this time).
If the cell charge enable
function is switched ON
AND V_CELL > V_CE
OR
Charge enable function is
switched OFF
If the cell charge enable
function is switched ON
AND
V_CELL < V_CE
— The X3100/X3101 initiates a reset operation that takes the longer of
T_{OV +} 200ms or T_UV + 200ms to complete. Do not write to the FET control
bits during this time.
— The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by
writing a “1” to the OVPC bit in the control register.
— The battery cells now receive charge via the charge FET and diode D1
across the discharge FET (which is OFF).
— The X3100/X3101 monitors the V_CELL voltage to determine whether or not it
has risen above V_UVR.
— Charge/discharge of the battery cells via P+ is no longer permitted (Charge
FET and discharge FET are held OFF).
— (Charging may re-commence only when the Cell Charge Enable function is
switched OFF - See Sections: “Configuration Register” page 4, and “Sleep
mode” page 17.)
— The voltage of all of the battery cells (V_CELL), have risen above V_UVR.
— The internal Over-discharge release timer begins counting down.
— The X3100/X3101 is still in over-discharge protection mode.
— The internal over-discharge release timer continues counting for t_UVR seconds.
— The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t_UVR. Other-
wise recovery is based on two successive samples about 120ms apart.
— The internal over-discharge release timer times out, AND V_CELL is still above V_UVR.
— The device returns from over-discharge protection mode, and is now in normal operation mode.
— The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.
— The discharge FET is can now be switched ON (UVP/OCP = V_SS) by the microcontroller by writing a “1” to
the UVPC bit of the control register.
— The status of the charge FET remains unaffected (ON)
— The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
18
FN8110.1
January 3, 2008