X3100-01 Datasheet, PDF (19/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Over-Current Protection
In addition to monitoring the battery cell voltages, the
X3100 and X3101 continually monitor the voltage
VCS₂₁ (VCS₂ - VCS₁) across the current sense resis-
tor (R_SENSE). If VCS₂₁ > V_OC for a time exceeding
T_OC, then the device enters over-current protection
mode (Figure 7). In this mode, the X3100 and X3101
automatically switch the discharge FET OFF
(UVP/OCP = Vcc) and hence prevent current from
flowing through the terminals P+ and P-.
Figure 5. Over-Current Protection
P+
Q2
I_LMON
D1
OVP/LMON
X3100/X3101
V_RGO
Q10
R_OCR
(Load)
FET Control
Circuitry
VSS
VCS1 VCS2
P-
R_SENSE
The 5VDC voltage regulator output (V_RGO) is always
active during an over-current protection mode.
Once the device enters over-current protection mode,
the X3100 and X3101 begin a load monitor state. In
the load monitor state, a small current (I_LMON = 7.5µA
typ.) is passed out of pin OVP/LMON in order to deter-
mine the load resistance. The load resistance is the
impedance seen looking out of pin OVP/LMON,
between terminal P+ and pin VSS (See Figure 5.)
If the load resistance > R_OCR (I_LMON = 0µA) for a time
exceeding T_OCR, then the X3100 or X3101 is released
from over-current protection mode. The discharge FET
is then automatically switched ON (UVP/OCP = Vss)
by the X3100 or X3101, unless the status of UVP/OCP
has been changed in control register (by manipulating
bit UVPC) during the over-current protection mode.
T_OC/T_OCR are varied using a capacitor (C_OC) con-
nected between pin OCT and VSS. A list of typical
delay times is shown in Table 23. Note that the value
C_OC should be larger than 1nF.
The delay T_OC and T_OCR that results from a particular
capacitance C_OC can be approximated by the follow-
ing equations:
T_OC (ms) ≈ 10,000 x C_OC (µF)
T_OCR (ms) ≈ 10,000 x C_OC (µF)
Table 23. Typical Over-Current Delay Times
Symbol Description
T_OC Over-current
detection delay
T_OCR Over-current
release time
C_OC
Delay
0.001µF 10ms (Typ)
0.001µF 10ms (Typ)
The value of V_OC can be selected from the values
shown in Table 6, by setting bits VOC1, VOC0 in the
configuration register using the WCFIG command.
Note: If the Charge FET is turned off, due to an over-
charge condition or by direct command from the micro-
controller, the cells are not in an undervoltage
condition and the pack has a load, then excessive cur-
rent may flow through Q10 and diode D1. To eliminate
this effect, the gate of Q10 can be turned off by the
microcontroller through an unused X3101 cell balance
output, or directly from a microcontroller port instead of
connecting to V_RGO.
19
FN8110.1
January 3, 2008