X3100-01 Datasheet, PDF (12/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier.
These are x10, x25, x80 and x160. For more detail,
see section “Current Monitor Function” on page 21.
Table 14. Current Sense Gain Control
Control Register Bits
CSG1
CSG0
Operation
0
0
Set current sense gain = x10
0
1
Set current sense gain = x25
1
0
Set current sense gain = x80
1
1
Set current sense gain = x160
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge
and discharge externally, via the SPI port. These bits
control the OVP/LMON and UVP/OCP pins, which in turn
control the external power FETs.
Using P-channel power FETs ensures that the FET is
on when the pin voltage is low (Vss), and off when the
pin voltage is high (Vcc).
OVP/LMON and UVP/OCP can be controlled by using
the WCNTR Instruction to set bits OVPC and UVPC in
the Control register (See page 11).
Table 15. UVP/OVP Control
Control Register Bits
OVPC
UVPC
Operation
1
x
Pin OVP = V_SS (FET ON)
0
x
Pin OVP = V_CC (FET OFF)
x
1
Pin UVP = V_SS (FET ON)
x
0
Pin UVP = V_CC (FET OFF)
It is possible to set/change the values of OVPC and
UVPC during a protection mode. A change in the state
of the pins OVP/LMON and UVP/OCP, however, will
not take place until the device has returned from the
protection mode.
Cell Voltage Balance Control (CBC1-CBC4)
This function can be used to adjust individual battery
cell voltage during charging. Pins CB1 - CB4 are used
to control external power switching devices. Cell volt-
age balancing is achieved via the SPI port.
Table 16. CB1—CB4 Control
Control Register Bits
CBC4 CBC3 CBC2 CBC1
x
x
x
1
x
x
x
0
x
x
1
x
x
x
0
x
x
1
x
x
x
0
x
x
1
x
x
x
0
x
x
x
Operation
Set CB1 = V_CC (ON)
Set CB1=V_SS (OFF)
Set CB2 = V_CC (ON)
Set CB2 = V_SS (OFF)
Set CB3 = V_CC (ON)
Set CB3 = V_SS (OFF)
Set CB4 = V_CC (ON)
Set CB4 = V_SS (OFF)
CB1 - CB4 can be controlled by using the WCNTR In-
struction to set bits CBC1 - CBC4 in the control register
(Table 16).
STATUS REGISTER
The status of the X3100 or X3101 can be verified by
using the RDSTAT command to read the contents of
the Status Register (Table 17).
Table 17. Status Register.
76543
2
0 0 0 0 0 CCES+
OVDS
1
UVDS
0
VRGS+
OCDS
The function of each bit in the status register is shown
in Table 18.
Bit 0 of the status register (VRGS+OCDS) actually
indicates the status of two conditions of the X3100 or
X3101. Voltage Regulator Status (VRGS) is an inter-
nally generated signal which indicates that the output
of the Voltage Regulator (VRGO) has reached an out-
put of 5VDC ± 0.5%. In this case, the voltage regulator
is said to be “tuned”. Before the signal VRGS goes low
(i.e. before the voltage regulator is tuned), the voltage
at the output of the regulator is nominally 5VDC ± 10%
(See section “Voltage Regulator” on page 22.) Over-
current Detection Status (OCDS) is another internally
generated signal which indicates whether or not the
X3100 or X3101 is in over-current protection mode.
Signals VRGS and OCDS are logically OR’ed together
(VRGS + OCDS) and written to bit 0 of the status reg-
ister (See Table 18, Table 17 and Figure ).
12
FN8110.1
January 3, 2008