X3100-01 Datasheet, PDF (23/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
The 4kbit EEPROM array can be accessed by the SPI
port at any time, even during a protection mode, except
during sleep mode. After power is applied to VCC of the
X3100 or X3101, EEREAD and EEWRITE Instructions
can be executed only after times t_PUR (power-up to
read time) and t_PUW (power-up to write time) respec-
tively.
IDLock is a programmable locking mechanism which
allows the user to lock data in different portions of the
EEPROM memory space, ranging from as little as one
page to as much as 1/2 of the total array. This is useful
for storing information such as battery pack serial
number, manufacturing codes, battery cell chemistry
data, or cell characteristics.
EEPROM Write Enable Latch
The X3100 and X3101 contain an EEPROM “Write
Enable” latch. This latch must be SET before a write to
EEPROM operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the
latch (Figure 9). This latch is automatically reset upon a
power-up condition and after the completion of a byte or
page write cycle.
IDLock Memory
Intersil’s IDLock memory provides a flexible mecha-
nism to store and lock battery cell/pack information.
There are seven distinct IDLock memory areas within
the array which vary in size from one page to as much
as half of the entire array.
Prior to any attempt to perform an IDLock operation,
the WREN instruction must first be issued. This
instruction sets the “Write Enable” latch and allows the
part to respond to an IDLock sequence. The EEPROM
memory may then be IDLocked by writing the SET IDL
instruction (Table 30 and Figure 17), followed by the
IDLock protection byte.
Table 28. IDLock Partition Byte Definition
IDLock Protection EEPROM Memory Address
Bytes
IDLocked
0000 0000
None
0000 0001
000h - 07Fh
0000 0010
0000 0011
0000 0100
080h - 0FFh
100h - 17Fh
180h - 1FFh
0000 0101
0000 0110
0000 0111
000h - 0FFh
000h - 00Fh
1F0h - 1FFh
The IDLock protection byte contains the IDLock bits
IDL2-IDL0, which defines the particular partition to be
locked (Table 28). The rest of the bits [7:3] are unused
and must be written as zeroes. Bringing CS HIGH
after the two byte IDLock instruction initiates a nonvola-
tile write to the status register. Writing more than one
byte to the status register will overwrite the previously
written IDLock byte.
Once an IDLock instruction has been completed, that
IDLock setup is held in a nonvolatile IDLock Register
(Table 29) until the next IDLock instruction is issued. The
sections of the memory array that are IDLocked can be
read but not written until IDLock is removed or changed.
Table 29. IDLock Register
76543
00000
Note: Bits [7:3] specified to be “0’s”
21
0
IDL2 IDL1 IDL0
X3100/X3101 SPI SERIAL COMMUNICATION
The X3100 and X3101 are designed to interface
directly with the synchronous Serial Peripheral Inter-
face (SPI) of many popular microcontroller families.
This interface uses four signals, CS, SCK, SI and SO.
The signal CS when low, enables communications
with the device. The SI pin carries the input signal and
SO provides the output signal. SCK clocks data in or
out. The X3100 and X3101 operate in SPI mode 0
which requires SCK to be normally low when not
transferring data. It also specifies that the rising edge
of SCK clocks data into the device, while the falling
edge of SCK clocks data out.
This SPI port is used to set the various internal regis-
ters, write to the EEPROM array, and select various
device functions.
The X3100 and X3101 contain an 8-bit instruction
register. It is accessed by clocking data into the SI
input. CS must be LOW during the entire operation.
Table 30 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock, and then start it again to resume opera-
tions where left off.
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FN8110.1
January 3, 2008