X3100-01 Datasheet, PDF (20/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
Figure 6. Over-Current Protection Mode—Event Diagram
Normal Operation Mode
Over-Current Protection Mode
B+
P+
P+ = (RLOAD+RSENSE) x ILMON
Normal Operation Mode
V_OC
VCS₂
T_OC
UVP/OCP
Event
0
1
2
T_OCR
3
4
Voc
V_SS
V_CC
V_SS
Table 24. Over-Current Protection Mode—Event Diagram Description
Event
[0,1)
[1]
(1,2)
[2]
(2,3)
Event Description
— Discharge FET is ON (OCP = Vss). Battery cells are permitted to discharge.
— VCS₂₁ (VCS₂ - VCS₁) is less than the over-current threshold voltage (V_OC).
— The device is in normal operation mode (i.e. not in a protection mode).
— Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 6.).
— The positive battery terminal voltage (P+) falls, and VCS₂₁ exceeds V_OC.
— The internal over-current detection delay timer begins counting down.
— The device is still in Normal Operation Mode
The internal Over-current detection delay timer continues counting for T_OC seconds.
— The internal over-current detection delay timer times out, AND VCS₂₁ is still above V_OC.
— The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).
— The device now begins a load monitor state by passing a small test current (I_LMON = 7.5µA) out of pin
OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < R_OCR) still exists across
P+/P-.
— The device has now entered over-current protection mode.
— It is possible to change the status of UVPC and OVPC in the control register, although the status of pins
UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection mode.
— The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over-
current condition is still present across the battery terminals P+/P-.
20
FN8110.1
January 3, 2008