X3100-01 Datasheet, PDF (35/41 Pages) Intersil Corporation – Cell Balancing Control

X3100, X3101
POWER-UP TIMING
Symbol
t_PUR(6)
t_PUW1(6)
t_PUW2(6)
Parameter
Power-up to SPI read operation (RDSTAT, EEREAD STAT)
Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR)
Power-up to SPI write operation (WCNTR - bits 10 and 11)
Min.
Max.
T_OC + 2ms
T_OC + 2ms
T_OV + 200ms
or
T_UV + 200ms⁽⁷⁾
Notes: (6) t_PUR, t_PUW1 and t_PUW2 are the delays required from the time V_CC is stable until a read or write can be initiated. These parameters are
not 100% tested.
(7) Whichever is longer.
CAPACITANCE T_A = +25°C, f = 1 MHz, V_RGO = 5V
Symbol
Parameter
C_OUT⁽⁸⁾
C_IN⁽⁸⁾
Output capacitance (SO)
Input capacitance (SCK, SI, CS)
Notes: (8) This parameter is not 100% tested.
Max.
8
6
Units
pF
pF
Conditions
V_OUT = 0V
V_IN = 0V
Equivalent A.C. Load Circuit
5V
SO
3025Ω
2061Ω
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
0.5 - 4.5V
10ns
2.5V
35
FN8110.1
January 3, 2008