ISL6329 Datasheet, PDF (7/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
Functional Pin Descriptions (Continued)
PIN NAME
BOOT1, BOOT2
LGATE1, LGATE2
GVOT
VDDPWRGD
PWROK
PWM3, PWM4, PWM5,
PWM6
PHASE_NB
UGATE_NB
BOOT_NB
LGATE_NB
PVCC
I2C_ADDR
PIN NUMBER
DESCRIPTION
38, 34
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
37, 35
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
36
The power supply pin for the multiphase internal MOSFET drivers. In normal operation, this pin is
shorted to the PVCC pin. While in PSI mode, this pin is tied to the output of the internal LDO for Gate
Drive Voltage Optimization. Decouple this pin with a quality 2.2μF ceramic capacitor.
41
During normal operation, this pin indicates whether both output voltages are within specified overvoltage
and undervoltage limits. If either output voltage exceeds these limits or a reset event occurs (such as an
overcurrent event), the pin is pulled low. This pin is always low prior to the end of soft-start.
42
System wide Power Good input signal. If this pin is low, the two SVI bits are decoded to determine the
“metal VID”. When pin is high, the SVI is actively running its protocol.
46, 45, 44, 43 Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver IC if 3,
4, 5, or 6-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to
disable them. Channels must be disabled in decremental order.
47
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return path for the
upper MOSFET drive. This pin is used to monitor the voltage drop across the upper MOSFET for
overcurrent protection.
48
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
49
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
50
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
51
The power supply pin for the internal MOSFET drivers. Connect this pin to +12V. This pin is the input to
the internal LDO for GVOT. Decouple this pin with a quality 1.0μF ceramic capacitor.
52
A resistor tied from this pin to either ground or VCC will set the I²C address. There are eight I²C
programmable addresses.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6329CRZ
ISL6329 CRZ
0 to +70
60 Ld 7x7 QFN
L60.7x7
ISL6329IRZ
ISL6329 IRZ
-40 to +85
60 Ld 7x7 QFN
L60.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6329. For more information on MSL please see techbrief TB363.
7
FN7800.0
April 19, 2011