ISL6329 Datasheet, PDF (20/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
Initialization
Prior to initialization, proper conditions must exist on the EN, VCC,
PVCC, ISEN2-, ISEN3-, ISEN4-, ISEN5-, and ISEN6- pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts VDDPWRGD.
Power-On Reset
The ISL6329 requires VCC, PVCC and GVOT inputs to exceed their
rising POR thresholds before the ISL6329 has sufficient bias to
guarantee proper operation.
The bias voltage applied to VCC must reach the internal power-on
reset (POR) rising threshold. Once this threshold is reached, the
ISL6329 has enough bias to begin checking the driver POR
inputs, EN, and channel detect portions of the initialization cycle.
Hysteresis between the rising and falling thresholds assure the
ISL6329 will not advertently turn off unless the bias voltage
drops substantially (see “Electrical Specifications” on page 9).
The bias voltage applied to the PVCC pin powers the internal
MOSFET drivers of each output channel. In order for the ISL6329
to begin operation, the PVCC input must exceed its POR rising
threshold to guarantee proper operation of the internal drivers.
Hysteresis between the rising and falling thresholds assure that
once enabled, the ISL6329 will not inadvertently turn off unless
the PVCC bias voltage drops substantially (see “Electrical
Specifications” on page 9). Depending on the number of active
CORE channels determined by the Phase Detect block, the
external driver POR checking is supported by the Enable
Comparator.
Enable Comparator
The ISL6329 features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The enable
comparator holds the ISL6329 in shutdown until the voltage at
EN rises above 0.86V. The enable comparator has about 110mV
of hysteresis to prevent bounce. It is important that the driver ICs
reach their rising POR level before the ISL6329 becomes
enabled. The schematic in Figure 12 demonstrates sequencing
the ISL6329 with the ISL66XX family of Intersil MOSFET drivers,
which require 12V bias.
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for calculating
the proper resistor values. This will prevent improper sequencing
events from creating false trips during soft-start.
If the controller is configured for 1- or 2-phase CORE operation,
then the resistor divider can be used for sequencing the
controller with another voltage rail. The resistor divider to EN
should be selected using a similar approach as the previous
driver discussion.
Phase Detection
The ISEN2-, ISEN3-, ISEN4-, ISEN5-, and ISEN6- pins are
monitored prior to soft-start to determine the number of active
CORE channel phases.
If ISEN6- is tied to VCC, the controller will configure the channel
firing order and timing for 5-phase operation. If ISEN6- and
ISEN5- are tied to VCC, the controller will set the channel firing
order and timing for 4-phase operation. If ISEN6-, ISEN5- and
ISEN4- are tied to VCC, the controller will set the channel firing
order and timing for 3-phase operation. If ISEN6-, ISEN5-, ISEN4-
and ISEN3- are tied to VCC, the controller will set the channel
firing order and timing for a 2-phase operation. The controller will
configure itself as a single phase regulator if ISEN6-, ISEN5-,
ISEN4-, ISEN3- and ISEN2- are tied to VCC (see “PWM Operation”
on page 13 for details).
Soft-Start Output Voltage Targets
Once the POR and Phase Detect blocks and enable comparator
are satisfied, the controller will begin the soft-start sequence and
will ramp the CORE and NB output voltages up to the SVI
interface designated target level. Prior to soft-starting both CORE
and NB outputs, the ISL6329 must check the state of the SVI
interface inputs to determine the correct target voltages for both
outputs. When the controller is enabled, the state of the SVD and
SVC inputs are checked and the target output voltages set for
both CORE and NB outputs are set by the DAC (see “Serial VID
Interface (SVI)” on page 15). These targets will only change if the
EN signal is pulled low or after a POR reset of VCC.
Soft-Start
The soft-start sequence is composed of three periods, as shown
in Figure 11. At the beginning of soft-start, the DAC immediately
obtains the output voltage target. A 100μs fixed delay time, TDA,
proceeds the output voltage rise. After this delay period the
ISL6329 will begin ramping both CORE and NB output voltages
to the programmed DAC level. The amount of time required to
ramp the output voltage to the final DAC voltage is referred to as
TDB, and can be calculated as shown in Equation 20.
TDB = -V----^D----^A----^C--
SR_SS
(EQ. 20)
Where the Soft-Start Slew Rate (SR_SS)defaults to 2.8mV/μsec
(typical). This slew rate, however, is programmable through the
I²C interface.
After the DAC voltage reaches the final VID setting, PGOOD will
be set to high.
V_NB
400mV/DIV
V_CORE
400mV/DIV
EN
5V/DIV
TDA
TDB
VDDPWRGD
5V/DIV
100µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
20
FN7800.0
April 19, 2011