ISL6329 Datasheet, PDF (24/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
The STOP (P) condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 16. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit.
Data is transferred with the most significant bit first (MSB) and
the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses. The
ninth pulse is the acknowledge bit (A). After the start condition,
the master sends 7 slave address bits and a R/W bit during the
next 8-clock pulses. During the ninth clock pulse, the device that
recognizes its own address holds the data line low to
acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data as described in Figure 17.
SCL
1
2
8
9
SDA
START
MSB
ACKNOWLEDGE
FROM SLAVE
FIGURE 17. ACKNOWLEDGE ON THE I²C BUS
ISL6329 I²C Slave Address
All devices on the I²C bus must have a 7-Bit I²C address in order
to be recognized. There are 8 selectable address available with
the ISL6329. To program an address, a resistor must be tied
from the I2C_ADDR pin (Pin 52) to either ground or VCC. The
resistor value will determine the address.
TABLE 4. I²C ADDRESS PROGRAMMING
RESISTOR TIED TO
RESISTOR VALUE
ADDRESS
Ground
0Ω
1000_110
Ground
20kΩ
1010_110
Ground
50kΩ
1001_110
Ground
100kΩ
1011_110
VCC
0Ω
1010_110
VCC
20kΩ
1010_111
TABLE 4. I²C ADDRESS PROGRAMMING (Continued)
RESISTOR TIED TO
RESISTOR VALUE
ADDRESS
VCC
50kΩ
1011_110
VCC
100kΩ
1011_111
Communicating Over the I²C Bus
Two transactions are supported on the I²C interface:
1. Write register
2. Read register from current address.
All transactions start with a control byte sent from the I²C master
device. The control byte begins with a Start condition, followed by
7-bits of slave address. The last bit sent by the master is the R/W
bit and is 0 for a write or 1 for a read. If any slaves on the I²C bus
recognize their address, they will Acknowledge by pulling the
serial data line low for the last clock cycle in the control byte. If
no slaves exist at that address or are not ready to communicate,
the data line will be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL6329 acknowledges it,
the 2nd byte sent by the master must be a register address byte.
This register address byte tells the ISL6329 which one of the
internal registers it wants to write to or read from. The address of
the first internal register, RGS0, is 0000_0000. This register sets
the Northbridge Offset, Overvoltage trip point and Power-good trip
level. The address of the second internal register, RGS1, is
0000_0001. This register sets the Core Offset, Overvoltage trip
point and Power-good trip level. The address of the third register,
RGS2, is 0000_0010. The third register is for programming of the
Power Savings Mode features. The fourth register, RGS3
(0000_0011) is Reserved. The fifth register, RGS4 (0000_0100), is
for Phase Control and the GVOT voltage. The sixth register, RGS5
(0000_0101), is used to set minimum phases for PSI and APD and
has droop programmability. The seventh register, RGS6
(0000_0110), controls the VID on the Fly slew rate, and various
APA programming. It is important to note that RGS4, RGS5 and
RGS6 can only be written to when the PWROK signal to the
ISL6329 is low. Otherwise, once the ISL6329 receives a correct
register address byte, it responds with an acknowledge.
TABLE 5. I²C REGISTER FUNCTIONS
REGISTER ADDRESS
FUNCTIONS
RGS0 0000_0000 Northbridge DAC Offset, OVP, PGOOD
RGS1 0000_0001
Core DAC Offset, OVP, PGOOD
RGS2 0000_0010
PSI Mode Functions
RGS3 0000_0011
Reserved
RGS4 0000_0100
Phase Control and GVOT
RGS5 0000_0101 Min Num Phases and Droop Functions
RGS6 0000_0110
VOF Slew Rate and APA Functions
Writing to the Internal Registers
In order to change any of the operating parameters via the I²C
bus, the internal registers must be written to. The five registers
inside the ISL6329 can be written individually with separate
write transactions or sequentially with one write transaction.
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FN7800.0
April 19, 2011