ISL6329 Datasheet, PDF (15/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
I_AVG(T)
I_{AVG_TCOMP}
R₁
R_NTC
TCOMP1
TCOMP2
R₂
R_T(T)
R_TC = R_T(25°C)
R₃
RT(T)
=
R3
+
----------------------1------------------------
---------------1---------------- + ---1----
R1 + RNTC R2
FIGURE 5. AVERAGE CURRENT TEMPERATURE COMPENSATION
Temperature Compensated Current Sensing
As the load increases, the conduction losses in the output
inductors will cause the temperature of the inductors to rise. As
the inductor temperature rises, the DCR of the output inductors
will also rise. An increase in the DCR will result in an increase in
the sensed current even if the load current remains constant. To
counteract this error in the sensed current, the ISL6329 features
a temperature compensating circuit that utilizes an NTC resistor
to adjust the average current as inductor temperature increases.
Figure 5 shows the implementation of the ISL6329 average
current temperature compensation. The temperature dependent
resistor, R_T(T), is a combination of resistors and an NTC which
create an approximate linearization of the NTC resistor (refer to
Equation 12). Resistors R₁, R₂ and R₃ should be adjusted so that
Equation 13 is satisfied.
R_T(T)
=
R₃
+
---------------------1-----------------------
--------------1--------------- + ---1---
R₁ + R_NTC R₂
(EQ. 12)
R_T(T)
=
D-----C-----R-----(_--2----5---°_---C-----)
DCR(T)
⋅
R_T
C
(EQ. 13)
Where R_TC = R_T(25°C)
LOAD MONITORING
The TCOMP2 pin can be utilized to monitor the load current. The
voltage across the R_TC resistor is a temperature compensated
representation of the load current. The load current is given by
Equation 14.
I_LOAD
=
8
⋅
V-----_{T---C----O-----M-----P----2-}
R_TC
⋅
R-----_{I--S----E----N--}
DCR
(EQ. 14)
Where R_ISEN is the current sense resistor value and DCR is the
DC resistance of the output inductors. It is recommended that a
high impedance buffer be used when monitoring the voltage on
the TCOMP2 pin.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over multiple
devices and greater area. By doing this the designer avoids the
complexity of driving parallel MOSFETs and the expense of using
expensive heat sinks and exotic magnetic materials.
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to carry
about the same amount of current at any load level. To achieve
this, the currents through each channel must be sampled every
switching cycle. The sampled currents, I_n, from each active
channel are summed together and divided by the number of
active channels. The resulting cycle average current, I_AVG,
provides a measure of the total load-current demand on the
converter during each switching cycle. Channel-current balance is
achieved by comparing the sampled current of each channel to
the cycle average current, and making the proper adjustment to
each channel pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I_AVG, is compared with the Channel 1 sample,
I₁, to create an error signal I_ER.
V_COMP
+
PWM1
+
TO GATE
-
MODULATOR
RAMP
-
CONTROL
LOGIC
WAVEFORM
FILTER f(s)
I₆
I_ER
I_AVG
-
÷N
+
I₅
Σ
I₄
I₃
I₁
I₂
NOTE: Channels 2, 3, 4, 5 and 6 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
The filtered error signal modifies the pulse width commanded by
V_COMP to correct any unbalance and force I_ER toward zero. The
same method for error signal correction is applied to each active
channel.
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the processor
to directly drive the core voltage and Northbridge voltage reference
level within the ISL6329. The SVC and SVD states are decoded with
direction from the PWROK input as described in the sections that
follow. The ISL6329 uses a digital to analog converter (DAC) to
generate a reference voltage based on the decoded SVI value. See
Figure 7 for a simple SVI interface timing diagram.
Pre-PWROK METAL VID
At start-up, the controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the POR circuitry
is satisfied, the ISL6329 begins decoding the inputs per Table 1.
Once the EN input exceeds the rising enable threshold, the ISL6329
saves the Pre-PWROK metal VID value in an on-board holding
register and passes this target to the internal DAC circuitry.
15
FN7800.0
April 19, 2011