ISL6329 Datasheet, PDF (25/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
To write to a single register in the ISL6329, the master sends a
control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL6329, it sends a register
address byte representing the internal register to which it wants
to write. The ISL6329 will respond with an Acknowledge. The
master then sends a byte representing the data byte to be written
into the desired register. The ISL6329 will respond with an
Acknowledge. The master then issues a Stop condition,
indicating to the ISL6329 that the current transaction is
complete. Once this transaction completes, the ISL6329 will
immediately update and change the operating parameters on-
the-fly.
It is also possible to write to the all the registers sequentially. To
do this the master must write to register RGS0 first. This
transaction begins with the master sending a control byte with
the R/W bit set to 0. If it receives an Acknowledge from the
ISL6329, it sends the register address byte 0000_0000,
representing the internal register RGS0. The ISL6329 will
respond with an Acknowledge. After sending the data byte to
RGS0 and receiving an Acknowledge from the ISL6329, instead
of sending a Stop condition, the master sends the data byte to be
stored in register RGS1. After the ISL6329 responds with another
Acknowledge, the master can either send a Stop condition to
indicate that the current transaction is complete, or it can send
the data byte to be stored in register RGS2. After the ISL6329
responds with an Acknowledge and if the PWROK signal is low,
this process can continue with a byte being written to RGS4.
Once the last register is written to, the ISL6329 will respond with
an Acknowledge and the master would send a Stop condition,
completing the transaction. Once this transaction completes the
ISL6329 will immediately update and change the operating
parameters on-the-fly.
Reading from the Internal Registers
The ISL6329 has the ability to read from both registers
separately or read from them consecutively. Prior to reading from
an internal register, the master must first select the desired
register by writing to it and sending the register’s address byte.
This process begins by the master sending a control byte with the
R/W bit set to 0, indicating a write. Once it receives an
Acknowledge from the ISL6329, it sends a register address byte
representing the internal register it wants to read from
(0000_0000 for RGS1, 0000_0001 for RGS2, etc). The ISL6329
will respond with an Acknowledge. The master must then
respond with a Stop condition. After the Stop condition, the
master follows with a new Start condition, and then sends a new
control byte with the R/W bit set to 1, indicating a read. The
ISL6329 will then respond by sending the master an
Acknowledge, followed by the data byte stored in that register.
The master must then send a Not Acknowledge followed by a
Stop command, which will complete the read transaction.
It is also possible for all registers to be read consecutively. To do
this the master must read from register RGS1 first. This
transaction begins with the master sending a control byte with
the R/W bit set to 0. If it receives an Acknowledge from the
ISL6329, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6329 will
respond with an Acknowledge. The master must then respond
with a Stop condition. After the Stop condition the master follows
with a new Start condition, and then sends a new control byte
with the R/W bit set to 1, indicating a read. The ISL6329 will
then respond by sending the master an Acknowledge, followed
by the data byte stored in register RGS1. The master must then
send an Acknowledge, and after doing so, the ISL6329 will
respond by sending the data byte stored in register RGS2. The
master must then send another Acknowledge, which the
ISL6329 will respond to by sending the data byte stored in
register RGS3. The master must then send a Not Acknowledge
followed by a Stop command, which will complete the read
transaction.
Resetting the Internal Registers
The ISL6329’s internal I²C registers always initialize to the states
shown in Table 6 when the controller first receives power. Once
the voltage on the VCC pin rises above the POR rising threshold
level, these registers can be changed at any time via the I²C
interface. If the voltage on the VCC pin falls below the POR falling
threshold, the internal registers are automatically reset to their
initial states.
TABLE 6. I²C REGISTER INITIAL STATES
REGISTER
ADDRESS
INITIAL STATE
RGS0
0000_0000
0000_0000
RGS1
0000_0001
0000_0000
RGS2
0000_0010
0000_0001
RGS4
0000_0100
0111_1100
RGS5
0000_0101
0000_0000
RGS6
0000_0110
0010_0001
It is possible to reset the first three internal registers without
powering down the controller and without requiring the controller
to stop regulating and soft-start again. Simply write the initial
states to the internal registers over the I²C interface. To initialize
RGS4, PWROK must be low.
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FN7800.0
April 19, 2011