ISL6329 Datasheet, PDF (18/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
or down to the appropriate VID level. Finally, the ISL6329 will
then re-enter Power Savings Mode.
While in Power Savings Mode, the ISL6329 implements two
features that effectively enhance the efficiency of the regulator
even more. These features are Diode Emulation and Gate Voltage
Optimization.
DIODE EMULATION
While in Power Savings Mode, the active phases will behave as if they
are in a standard buck configuration. To accomplish this, the lower
MOSFET is turned on only while there is current flowing to the load. This
behavior emulates the diode in a standard buck. The conduction loss
across the R_DS(on) of the MOSFET, however, is much less than a diode,
resulting in a measurable power savings.
GATE VOLTAGE OPTIMIZATION
While in Power Savings Mode, the gate drive voltage for the lower
MOSFETs of the active phases is reduced from the nominal 12V
that is utilized in Normal mode to 5.75V. Lowering the gate drive
voltage can have an appreciable effect on the efficiency of the
converter.
In order to utilize 5V gate drive at all times, 5V should be tied to
the PVCC pin and the GVOT pin should be shorted to the PVCC
pin. This configuration will allow for 5V gate drive in all modes of
operation.
Voltage Regulation
The integrating compensation network shown in Figure 8 insures
that the steady-state error in the output voltage is limited only to
the error in the reference voltage and offset errors in the OFS
current source, remote-sense and error amplifiers. Intersil
specifies the guaranteed tolerance of the ISL6329 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V_COMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and regulate
the converter output so that the voltage at FB is equal to the
voltage at REF. This will regulate the output voltage to be equal to
Equation 15. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 8.
V_OUT = V_REF – V_OFS – V_DROOP
(EQ. 15)
The ISL6329 incorporates differential remote-sense amplification in
the feedback path. The differential sensing removes the voltage
error encountered when measuring the output voltage relative to the
controller ground reference point resulting in a more accurate
means of sensing output voltage.
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output voltage
can effectively be level shifted in a direction which works to
achieve a cost-effective solution can help to reduce the output-
voltage spike that results from fast load-current demand
changes.
The magnitude of the spike is dictated by the ESR and ESL of the output
capacitors selected. By positioning the no-load voltage level near the
upper specification limit, a larger negative spike can be sustained
without crossing the lower limit. By adding a well controlled output
impedance, the output voltage under load can effectively be level
shifted down so that a larger positive spike can be sustained without
crossing the upper specification limit.
EXTERNAL CIRCUIT
ISL6329 INTERNAL CIRCUIT
COMP
DROOP
CONTROL
C_C
R_C
FB
R_FB
+
(V_DROOP + V_OFS)
-
+
V_OUT
-
VSEN
RGND
I_AVG
I_OFS
-
V_COMP
+ _ERROR
AMPLIFIER
2k
∑
VID
DAC
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH
OFFSET ADJUSTMENT
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I_AVG, flows from FB
through a load-line regulation resistor R_FB. The resulting voltage
drop across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 16)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
shown in Equation 17.
V_OUT
=
V_R
E
F
–
V_OF
S
–
⎛
⎜
⎝
-I-^O-----^U----^T--
N
⋅
---D----C-----R-----
R_ISEN
⋅
K
⋅
⎞
R _{F B⎠⎟}
(EQ. 17)
In Equation 17, V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current of the
converter, K is the DC gain of the RC filter across the inductor (K
is defined in Equation 8), N is the number of active channels, and
DCR is the distributed inductor impedance value.
Droop Control
The DRPCTRL (Droop Control) pin is used to enable and/or
disable load line regulation on both the Core and Northbridge
regulators. A single resistor tied from the DRPCTRL pin to Ground
will program the ISL6329 to either enable or disable droop on
both Core and Northbridge simultaneously.
18
FN7800.0
April 19, 2011