ISL6329 Datasheet, PDF (28/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
Control. Bits 0 and 1 are for overriding analog programming of
NB droop control. Bits 2 and 3 are for adjusting the droop gain.
Bits 4 and 5 override the analog programming for number of
active phases in Power Savings Mode. This register can only be
written to when PWROK is LOW.
TABLE 11. BITS [7:0] REGISTER RGS5
Bits [7:6]
Reserved
Bits [5:4]
Number of Active Phases in Power Savings Mode
0x
No Action (Default)
10
Num Phases in PSI = 1
11
Num Phases in PSI = 2
Bits [3:2]
Core Droop Gain Adjust
00
Droop Current Gain = 1 (Default)
01
Droop Disabled
10
Droop Current Gain = 1/2
11
Droop Current Gain = 1/4
Bits [1:0]
Northbridge Droop Control Override
0x
No Action (Default)
10
Northbridge Droop Disabled
11
Northbridge Droop Enabled
The bits for Register RGS6 control some of the functionality of
the ISL6329 for VID on the Fly Slew Rate and APA. Bits 0 through
3 are reserved. Bit 4 selects whether APA is controlled by
monitoring the VSEN pin or the COMP pin. Bit 5 will
disable/enable APAL and APAH events. Bits 6 and 7 control the
VID on the Fly slew rate. This register can only be written to when
PWROK is Low.
TABLE 12. BITS [7:0] REGISTER RGS6
Bits [7:6]
00
01
10
11
VID on the Fly Slew Rate
2.8mV/μsec
5.6mV/μsec
7.5mV/μsec
9.4mV/μsec
Bit 5
Enable APAL and APAH Events
0
Disabled
1
ENABLED (Default)
Bit 4
VSEN or COMP APA Monitoring
0
Monitor VSEN (Default)
1
Monitor COMP
Bits [3:0]
Reserved
General Design Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills and
techniques referenced below. In addition to this guide, Intersil
provides complete reference designs that include schematics, bills
of materials, and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily on
the cost analysis which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board, whether through-hole components
are permitted, the total board space available for power-supply
circuitry, and the maximum amount of load current. Generally
speaking, the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount designs
will tend toward the lower end of this current range. If through-
hole MOSFETs and inductors can be used, higher per-phase
currents are possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase, but
these designs require heat sinks and forced air to cool the
MOSFETs, inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to current
conducted through the channel resistance (r_DS(ON)). In
Equation 23, I_M is the maximum continuous output current, I_PP
is the peak-to-peak inductor current (see Equation 2), and d is the
duty cycle (V_OUT/V_IN).
P_{LOW, 1}
=
r_DS(ON) ⋅
⎛
⎜
I--_{M---⎟⎞}
⎝ N⎠
2
⋅
(1
–
d)
+
I--_L---,---^2P_----P-----⋅_---(_--1-----–_-----d----)
12
(EQ. 23)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-MOSFET
body diode. This term is dependent on the diode forward voltage
at I_M, V_D(ON), the switching frequency, f_S, and the length of dead
times, t_d1 and t_d2, at the beginning and the end of the lower-
MOSFET conduction interval respectively.
P_{LOW, 2} = VD_(ON) ⋅ fS ⋅
⎛
⎜
⎝
I--M----
N
+
I--P--2---P--_{⎠⎟⎞}
⋅
td1
+
⎛
⎜
⎜
⎝
I--M----
N
–
I--P--2---P--_{⎠⎟⎟⎞}
⋅
td2
(EQ. 24)
The total maximum power dissipated in each lower MOSFET is
approximated by the summation of P_LOW,1 and P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper-MOSFET
losses are due to currents conducted across the input voltage
(V_IN) during switching. Since a substantially higher portion of the
upper-MOSFET losses are dependent on switching frequency, the
power calculation is more complex. Upper MOSFET losses can be
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FN7800.0
April 19, 2011