ISL6329 Datasheet, PDF (31/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
4. Select new values, R_1,NEW and R_2,NEW, for the time constant
resistors based on the original values, R_1,OLD and R_2,OLD,
using Equations 33 and 34.
R1, _NEW
=
R1, _OLD ⋅
D------V-----1---
DV2
(EQ. 33)
R2, _NEW
=
R2, _OLD ⋅
D------V-----1---
DV2
(EQ. 34)
5. Replace R₁ and R₂ with the new values and check to see that
the error is corrected. Repeat the procedure if necessary.
Loadline Regulation Resistor
The loadline regulation resistor, labeled R_FB in Figure 8, sets
the desired loadline required for the application. Equation 35
can be used to calculate R_FB.
R_FB
=
-----------V-----^D----^R----^O----^O-----^P----^M----^A----^X-------------
⎝⎜⎛_---I----^{O----------U--------TN------M----------A--------X-------â‹}_{---D-----C-----R----}⎠⎟⎞_-
R_ISEN
⋅
K
(EQ. 35)
If no loadline regulation is required, the DRPCTRL pin can be
used to enable or disable droop on the Core and Northbridge
regulators independently. To choose the value for R_FB with no
loadline, please refer to “Compensation Without Loadline
Regulation” on page 31.
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar manner to
a peak current mode controller because the two poles at the
output filter L-C resonant frequency split with the introduction of
current information into the control loop. The final location of
these poles is determined by the system function, the gain of the
current signal, and the value of the compensation components,
R_C and C_C.
C₂ (OPTIONAL)
R_C ^CC
COMP
FB
ISL6329
R_FB
VSEN
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6329 CIRCUIT
Since the system poles and zero are affected by the values of the
components that are meant to compensate them, the solution to
the system equation becomes fairly complicated. Fortunately,
there is a simple approximation that comes very close to an
optimal solution. Treating the system as though it were a voltage-
mode regulator, by compensating the L-C poles and the ESR zero
of the voltage mode approximation, yields a solution that is
always stable with very close to ideal transient performance.
Select a target bandwidth for the compensated system, f₀. The
target bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-channel
switching frequency. The values of the compensation
components depend on the relationships of f₀ to the L-C pole
frequency and the ESR zero frequency. For each of the following
three, there is a separate set of equations for the compensation
components.
In Equation 36, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent series resistance of the bulk
output filter capacitance; and V_PP is the peak-to-peak sawtooth
signal amplitude as described in the “Electrical Specifications”
on page 9.
Once selected, the compensation values in Equation 36 assure a
stable converter with reasonable transient performance. In most
cases, transient performance can be improved by making
adjustments to R_C. Slowly increase the value of R_C while
observing the transient performance on an oscilloscope until no
further improvement is noted. Normally, C_C will not need
adjustment. Keep the value of C_C from Equation 36 unless some
performance issue is noted.
The optional capacitor, C₂, is sometimes needed to bypass noise
away from the PWM comparator (see Figure 23). Keep a position
available for C₂, and be prepared to install a high-frequency
capacitor of between 22pF and 150pF in case any leading edge
jitter problem is noted.
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C = R_FB ⋅ ^2-----â‹---^π-----^â‹---0f--⁰-.--6-^â‹--6-V----_â‹-^p--V-^p---_I-^â‹-_N-------L----^â‹---C---
C_C
=
--------------0---.--6---6-----^â‹---V----^I--^N----------------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C
=
R_F
B
⋅
-V----^P----^P-----^â‹---⁽--2-----^â‹---^π----⁾--²----^â‹-----f-⁰--²-----^â‹---L-----^â‹---C---
0.66 ⋅ V_IN
C_C
=
------------------------------0----.-6----6-----^â‹---V----^I--^N--------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_PP ⋅ R_FB ⋅ L ⋅ C
(EQ. 36)
Case 3:
f₀ > _2-----â‹---_π-----_â‹---C--1----_â‹---E----S-----R---
R_C = R_FB ⋅ _0-2---.--6^â‹---6^π-----_⋅â‹---f-V-⁰---_I--^â‹_N---V--_â‹--^p-E--^p---S--^â‹--R-L--
C_C
=
----0----.--6---6-----^â‹---V----^I--^N-----^â‹---E----S-----R------^â‹-------C-------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀ ⋅ L
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled as a
voltage-mode regulator with two poles at the L-C resonant
31
FN7800.0
April 19, 2011