ISL6329 Datasheet, PDF (27/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
TABLE 8. BITS [5:0] REGISTER RGS0 and RGS1 (VOLTAGE
MARGINING OFFSET) (Continued)
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
V_OFFSET
VO5 VO4 VO3 VO2 VO1 VO0
(mV)
1
1
1
1
1
1
-25
0
0
0
0
0
0
0
0
0
0
0
0
1
25
0
0
0
0
1
0
50
0
0
0
0
1
1
75
0
0
0
1
0
0
100
0
0
0
1
0
1
125
0
0
0
1
1
0
150
0
0
0
1
1
1
175
0
0
1
0
0
0
200
0
0
1
0
0
1
225
0
0
1
0
1
0
250
0
0
1
0
1
1
275
0
0
1
1
0
0
300
0
0
1
1
0
1
325
0
0
1
1
1
0
350
0
0
1
1
1
1
375
0
1
0
0
0
0
400
0
1
0
0
0
1
425
0
1
0
0
1
0
450
0
1
0
0
1
1
475
0
1
0
1
0
0
500
0
1
0
1
0
1
525
0
1
0
1
1
0
550
0
1
0
1
1
1
575
0
1
1
0
0
0
600
0
1
1
0
0
1
625
0
1
1
0
1
0
650
0
1
1
0
1
1
675
0
1
1
1
0
0
700
0
1
1
1
0
1
725
0
1
1
1
1
0
750
0
1
1
1
1
1
775
The bits for Register RGS2 control some of the functionality of
the ISL6329 for Power Savings Mode. Bit0 selects whether diode
emulation is enabled in Power Savings Mode. Bits 1 and 2
control the number of PWM cycles between adding of phases
when exiting Power Savings Mode. Bits 3 and 4 control the
number of PWM cycles between dropping of phases when
entering Power Savings Mode. Bit 5 will disable/enable the DAC
offset when in Power Savings Mode. Bits 6 and 7 are reserved.
See Table 9 for a complete description of register RGS2 bits and
their functionality.
TABLE 9. BITS [7:0] REGISTER RGS2
Bits [7:6]
Reserved
Bit 5
Offset Enable in Power Savings Mode
0
ENABLED (Default)
1
DISABLED
Bits [4:3]
Number of PWM Cycles Between Dropping Phases
00
1 PWM Cycle (default)
01
2 PWM Cycles
10
4 PWM Cycles
11
0 PWM Cycles (All Phases Drop at Once)
Bits [2:1]
Number of PWM Cycles Between Adding Phases
00
1 PWM Cycle (Default)
01
2 PWM Cycles
10
4 PWM Cycles
11
0 PWM Cycles (All Phases Added at Once)
Bit 0
0
1
Diode Emulation in Power Savings Mode
Disabled
Enabled (Default)
Register RGS4 controls the number of active phases and the
GVOT level. It can only be written to when the PWROK signal is
low. Bit 7 is reserved. Bits 6 through 2 control the number of
active phases. It is important to note that is a bit is set to 1 then
all the lesser significant bits must also be set to 1 as well. Bits 1
and 0 control the GVOT voltage level. This register can only be
written to when PWROK is LOW.
TABLE 10. BITS [7:0] REGISTER RGS4
Bit 7
Reserved
Bits [6:2]
Active Phase Control
00000
Single Phase Regulator
00001
Two Phase Regulator
00011
Three Phase Regulator
00111
Four Phase Regulator
01111
Five Phase Regulator
11111
Six Phase Regulator (Default)
Bits [1:0]
GVOT Level
00
5.75V (Default)
01
6.75V
10
7.75V
11
11.2V
The bits for Register RGS5 control some of the functionality of
the ISL6329 for Power Savings Mode, Droop Gain, NB Droop
27
FN7800.0
April 19, 2011