ISL6329 Datasheet, PDF (5/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

Pin Configuration
ISL6329
ISL6329
(60 LD QFN)
TOP VIEW
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
COMP_NB 1
FB_NB 2
VSEN_NB 3
DRPCTRL 4
SVC 5
SVD 6
VDDIO 7
SCL 8
SDA 9
VCC 10
RSVD 11
OFS 12
OCP 13
TCOMP1 14
TCOMP2 15
61
GND
45 PWM4
44 PWM5
43 PWM6
42 PWROK
41 VDDPWRGD
40 PHASE1
39 UGATE1
38 BOOT1
37 LGATE1
36 GVOT
35 LGATE2
34 BOOT2
33 UGATE2
32 GND
31 EN
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
SVC
SVD
VDDIO
SCL
PIN NUMBER
1
2
3
4
5
6
7
8
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor tied to ground: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop
On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
Reference voltage for the SVI communication bus. Connect this pin to the system VDDIO and decouple
using a quality 0.1μF ceramic capacitor.
Connect this pin to the clock signal for the I²C bus, which is a logic level input signal. The clock signal
tells the controller when data is available on the I²C bus.
5
FN7800.0
April 19, 2011