ISL6329 Datasheet, PDF (23/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
recommended that if the maximum current spike load was
applied to the Core regulator that overcurrent protection
shutdown initiate after 1ms. This would require a 0.01μF
capacitor be tied to the OCP pin. To calculate the OCP capacitor,
use Equation 22.
C_OCP
=
2----0----μ_----A-----⋅_{---t--D----E----L---A----Y--}
2V
(EQ. 22)
NORTHBRIDGE REGULATOR OVERCURRENT
The Northbridge regulator does not incorporate dual OCP. When
the sensed current of the Northbridge exceeds 100μA,
Overcurrent Protection Shutdown is initiated. The overcurrent
shutdown for the Northbridge regulator will only disable the
MOSFET drivers for the Northbridge. Once 7 retry attempts have
been executed unsuccessfully, the controller will disable UGATE
and LGATE signals for both Core and Northbridge and will latch
off requiring a POR of VCC to reset the ISL6329.
OVERCURRENT PROTECTION IN POWER SAVINGS
MODE
While in Power Savings Mode, the OCP trip point will be lower
than when running in Normal Mode and there is no
accommodation for current throttling. Equation 21 (with N = 1 for
single phase PSI operation and with N = 2 for two phase PSI
operation) will yield the OCP trip point for the Core regulator
while in Power Savings mode.
If an overcurrent event should occur while the system is in Power
Savings Mode, the ISL6329 will restart in the Normal state with
the PSI_L bit set to 1.
Individual Channel Overcurrent Limiting
The ISL6329 has the ability to limit the current in each individual
channel of the Core regulator without shutting down the entire
regulator. This is accomplished by continuously comparing the
sensed currents of each channel with a constant 170μA OCL
reference current. If a channel’s individual sensed current
exceeds this OCL limit, the UGATE signal of that channel is
immediately forced low, and the LGATE signal is forced high. This
turns off the upper MOSFET(s), turns on the lower MOSFET(s),
and stops the rise of current in that channel, forcing the current
in the channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls back
below the 170μA reference.
I²C Bus Interface
The ISL6329 includes an I²C bus interface which allows for user
programmability of numerous operating parameters and
programmability of the Power Savings Mode feature. Some of
the parameters that can be adjusted through the I²C are:
1. Voltage Margining Offset: The DAC voltage can be offset in
25mV increments.
2. VDDPWRGD Trip Level: The PGOOD trip level for either the
Core regulator or the Northbridge regulator can be increased.
3. Overvoltage Trip Level: The OVP trip level of either the Core or
Northbridge regulator can be increased.
4. Core Droop Gain: The droop current can be decreased or
halted.
5. Power Savings Mode Options:
a. The number of phases to drop to in Power Savings Mode can
be programmed
b. The number of PWM cycles between dropping phases while
entering Power Savings Mode can be programmed.
c. The number of PWM cycles between adding phases when
exiting Power Savings Mode can be programmed.
d. Core Voltage Margining Offset can be Enabled or Disabled
while in Power Savings Mode.
e. The GVOT voltage level can be programmed
To adjust these parameters, data transmission to and from the
ISL6329 must take place through the two wire I²C bus interface.
The two wires of the I²C bus consist of the SDA line, over which all
data is sent, and the SCL line, which is a clock signal used to
synchronize sending/receiving of the data.
Both SDA and SCL are bidirectional lines, externally connected to a
positive supply voltage via a pull-up resistor. Pull-up resistor values
should be chosen to limit the input current to less then 3mA.
When the bus is free, both lines are HIGH. The output stages of
ISL6329 have an open drain/open collector in order to perform the
wired-AND function. Data on the I²C bus can be transferred up to
100Kbps in the standard-mode or up to 400Kbps in the fast-mode.
The level of logic “0” and logic “1” is dependent on associated value
of V_DD as per the “Electrical Specifications” table. One clock pulse is
generated for each data bit transferred. The ISL6329 is a “SLAVE
only” device, so the SCL line must always be controlled by an
external master.
It is important to note that the I²C interface of the ISL6329 only
works once the voltage on the VCC pin has risen above the POR
rising threshold. The I²C will continue to remain active until the
voltage on the VCC pin falls back below the falling POR threshold
level. All registers are reset on POR.
Data Validity
The data on the SDA line must be stable during the HIGH period
of the SCL, unless generating a START or STOP condition. The
HIGH or LOW state of the data line can only change when the
clock signal on the SCL line is LOW. Refer to Figure 15.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 15. DATA VALIDITY
START and STOP Conditions
Figure 16 shows a START (S) condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
23
FN7800.0
April 19, 2011