ISL6329 Datasheet, PDF (29/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
divided into separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-recovery
charge, Q_rr, and the upper MOSFET r_DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does not
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 25, the required time for this
commutation is t₁ and the approximated associated power loss
is P_UP,1.
P _{U P,1}
≈
V_IN
⋅
⎛
⎝
I--_M---
N
+
-I-^P--2--^P--_⎠⎞
⋅
⎛
⎜
t--_1--
⎞
⎟
⎝ ²âŽ 
⋅
f_S
(EQ. 25)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 26, the approximate
power loss is P_UP,2.
P_{UP, 2}
≈
V_IN
⋅
⎛
⎜
I--_M---
⎝N
–
I--_{P----P--⎟⎞}
2_⎠
⋅
⎛
⎜
⎝
t--_2--
⎞
⎟
2_⎠
⋅
f_S
(EQ. 26)
A third component involves the lower MOSFET reverse-recovery
charge, Q_rr. Since the inductor current has fully commutated to
the upper MOSFET before the lower-MOSFET body diode can
recover all of Q_rr, it is conducted through the upper MOSFET
across VIN. The power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 27)
Finally, the resistive part of the upper MOSFET is given in
Equation 28 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅
⎛
⎜
⎝
I--_{M---⎟⎞}
N⎠
2
⋅
d
+
I--_P----P--²_-
12
(EQ. 28)
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 25, 26, 27 and 28. Since the power equations depend
on MOSFET parameters, choosing the correct MOSFETs can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the PHASE node.
This reduces voltage stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 4V and its capacitance value can be chosen from
Equation 29:
C _{B O O T _CAP}
≥
----------Q-----^G----^A----^T---^E-----------
Δ V_{B O O T _CAP}
(EQ. 29)
Q_GATE=
Q-----_G-----1----•_{-----P----V-----C----C---}
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET at
V_GS1 gate-source voltage and N_Q1 is the number of control
MOSFETs. The ΔV_{BOOT_CAP} term is defined as the allowable
droop in the rail of the upper gate drive.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Gate Drive Voltage Versatility
The ISL6329 provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. The controller ties the
upper and lower drive rails together. Simply applying a voltage
from 5V up to 12V on PVCC sets both gate drive rail voltages
simultaneously.
Package Power Dissipation
When choosing MOSFETs, it is important to consider the amount
of power being dissipated in the integrated drivers located in the
controller. Since there are a total of three drivers in the controller
package, the total power dissipated by all three drivers must be
less than the maximum allowable power dissipation for the QFN
package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 34 for
thermal transfer improvement suggestions.
When designing the ISL6329 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P_{Qg_TOT}, due to the
gate charge of MOSFETs and the integrated driver’s internal
circuitry and their corresponding average driver current can be
estimated with Equations 30 and 31, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
P _{Q g _Q1}
=
3--
2
⋅
Q_G1
⋅
PVCC
⋅
F_SW
⋅
N_Q1
⋅
N_PHASE
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
(EQ. 30)
I_DR
=
⎛
⎝
3--
2
⋅
Q_G
1
⋅
N_Q
1
+
Q_G
2
Þ
N _{Q 2⎠⎞}
⋅ N_PHASE ⋅ F_SW + I_Q
(EQ. 31)
29
FN7800.0
April 19, 2011