ISL6329 Datasheet, PDF (32/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
frequency and a zero at the ESR frequency. A type III controller,
as shown in Figure 24, provides the necessary compensation.
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6329
VSEN
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to assure
adequate transient performance but not higher than 1/3 of the
switching frequency. The type-III compensator has an extra
high-frequency pole, f_HF. This pole can be used for added noise
rejection or to assure adequate attenuation at the error-amplifier
high-order pole and zero frequencies. A good general rule is to
choose f_HF = 10f₀, but it can be higher if desired. Choosing f_HF to
be lower than 10f₀ can cause problems with too much phase shift
below the system bandwidth.
R₁
=
R_FB
⋅ ------------C------^â‹---E----S-----R-------------
L ⋅ C – C ⋅ ESR
C₁
=
-----L-----^â‹---C-----^–-----C------^â‹---E----S-----R--
R_FB
C₂
=
--------------------------------------0---.--7---5-----^â‹---V----^I--^N---------------------------------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_PP
R_C
=
-V----^P----^P-----^â‹---^⎝⎛---2----^π---^⎠⎞---²-----^â‹---f--⁰----^â‹---f--^H----^F-----^â‹---L-----^â‹---C-----^â‹---R-----^F----^B--
0.75 ^⋠V_IN ^{⋅ (2 ⋅ π ⋅ f}_HF ^{⋅ L ⋅ C–1)}
(EQ. 37)
C_C
=
-------0---.--7---5-----^â‹---V----^I--^N-----^â‹---⁽---2----^â‹---^π-----^â‹---f--^H----^F-----^â‹-------L-----^â‹---C-----^–---1----⁾------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_PP
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equation 38,
R_FB is selected arbitrarily. The remaining compensation
components are then selected according to Equation 38.
In Equation 38, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent-series resistance of the bulk
output-filter capacitance; and V_PP is the peak-to-peak sawtooth
signal amplitude as described in “Electrical Specifications” on
page 9.
Case 1:
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C
=
R_F
B
⋅
2-----⋅_---π_-----⋅_---f--0----⋅_{---V-----p---p----}⋅_{--------L----}⋅_----C--
0.66 ⋅ V_IN
C_C = _2-----â‹---_π-----_â‹-0--V-.--6-_P--6--_P---^â‹--_â‹-V--R--^I--^N-_F---_B-----_â‹----f-₀--
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
2-----⋅^---π^-----⋅^---C--1----⋅^{---E----S-----R---}
R_C = R_FB ⋅ -V----^P----^P-----^â‹---⁽--20----.-^â‹_6---^π-6---⁾--_⋲----V^â‹----_I-f-_N0--²-----^â‹---L-----^â‹---C---
C_C
=
------------------------------0----.-6----6-----^â‹---V----^I--^N--------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_PP ⋅ R_FB ⋅ L ⋅ C
(EQ. 38)
Case 3:
f₀
>
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C
=
R_FB
⋅
-2-----^â‹---^π-----^â‹---f--⁰-----^â‹---V----^p---^p-----^â‹---L--
0.66 ⋅ V_IN ⋅ ESR
C_C
=
----0----.--6---6-----^â‹---V----^I--^N-----^â‹---E----S-----R------^â‹-------C-------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀ ⋅ L
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter limits the system transient response. The output
capacitors must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, ΔI, the load-current slew rate,
di/dt, and the maximum allowable output-voltage deviation under
transient loading, ΔV_MAX. Capacitors are characterized according
to their capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL and
ESR so that the total output-voltage deviation is less than the
allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount:
Δ
V
≈
E
S
L
⋅
-d---i
dt
+
E
S
R
⋅
Δ
I
(EQ. 39)
The filter capacitor must have sufficiently low ESL and ESR so
that ΔV < ΔV_MAX.
32
FN7800.0
April 19, 2011