ISL6329 Datasheet, PDF (19/38 Pages) Intersil Corporation – Dual PWM Controller Powering AMD SVI Split-Plane Processors

ISL6329
TABLE 3. DRPCTRL FUNCTIONALITY
RESISTOR VALUE
CORE DROOP
NB DROOP
100kΩ
Disabled
Disabled
50kΩ
Disabled
Enabled
20kΩ
Enabled
Enabled
0Ω
Enabled
Disabled
Output-Voltage Offset Programming
The ISL6329 allows the designer to accurately adjust the offset
voltage by connecting a resistor, R_OFS, from the OFS pin to VCC or
GND. When R_OFS is connected between OFS and VCC, the voltage
across it is regulated to 1.6V. This causes a proportional current
(I_OFS) to flow into the FB pin and out of the OFS pin. If R_OFS is
connected to ground, the voltage across it is regulated to 0.3V,
and I_OFS flows into the OFS pin and out of the FB pin. The offset
current flowing through the resistor between VDIFF and FB will
generate the desired offset voltage which is equal to the product
(I_OFS x R_FB). These functions are shown in Figures 9 and 10.
Once the desired output offset voltage has been determined, use
the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-0---.--3-----^×----R-----^F----^B--
V_OFFSET
(EQ. 18)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
-1---.--6-----^×----R-----^F----^B--
V_OFFSET
(EQ. 19)
VDIFF
-
V_{OFS RFB}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6329
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE PROGRAMMING
V_OUT
+
V_{OFS RFB}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
ISL6329
+
0.3V
-
-
1.6V
+
GND
GND
VCC
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING
Dynamic VID
The AMD processor does not step the output voltage commands
up or down to the target voltage, but instead passes only the
target voltage to the ISL6329 through the SVI interface. The
ISL6329 manages the resulting VID-on-the-Fly transition in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption. The ISL6329 slews the DAC at
2.8mV/μs until the DAC and target voltage are equal. Thus, the
total time required for a dynamic VID transition is dependent only
on the size of the DAC change. The slew rate can be adjusted
through the I²C interface (see “I²C Bus Interface” on page 23).
Advanced Adaptive Zero Shoot-Through
Deadtime Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFET body-
diode conduction, and to prevent the upper and lower MOSFETs
from conducting simultaneously. This is accomplished by ensuring
either rising gate turns on its MOSFET with minimum and sufficient
delay after the other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor
current). At this time the UGATE is released to rise. An auto-zero
comparator is used to correct the r_DS(ON) drop in the phase voltage
preventing false detection of the -0.3V phase level during r_DS(ON)
conduction period. In the case of zero current, the UGATE is released
after 35ns delay of the LGATE dropping below 0.5V. When LGATE
first begins to transition low, this quick transition can disturb the
PHASE node and cause a false trip, so there is 20ns of blanking
time once LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a PWM
falling edge and the subsequent UGATE turn-off. If either the
UGATE falls to less than 1.75V above the PHASE or the PHASE
falls to less than +0.8V, the LGATE is released to turn-on.
19
FN7800.0
April 19, 2011