82443ZX Datasheet, PDF (99/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
considered valid on the interface and hence when CS# can be asserted for CPU read leadoff cycles.
In the fastest timing mode, CS# can be asserted in clock three. This enables a 7 clock page hit
performance with CAS# Latency two devices and one clock MD to HD delay. This field controls
when the first assertion of CS# occurs for read cycles initiated by the CPU. This assertion may be
for a read, row activate or precharge command. The MA lines along with the command lines
(SRAS#, SCAS# and WE#) are driven in clock two, however the clock to output delay timing is
slower than the other modes. Use of this mode may require a lightly loaded SDRAM interface.
4.3.4 DRAMT Register Programming
Various EDO timing parameters are programmable in the 82443ZX. The ranges provide support
for the various loading configurations at 66 MHz. These are programmed via the DRAMT (DRAM
Timing) register. Only 60 ns EDO DRAMs are supported and at 66 MHz only. Thus, certain
parameters are fixed and are not programmable.
Table 4-13. EDO DRAM Timing Parameters
Parameter
RAS# Precharge
RAS# Pulse Width
RAS# to CAS# Delay
CAS# Precharge
CAS# Pulse Width
WE# Setup to CAS# Falling
WE# Hold from CAS# Falling
MA Setup to RAS#/CAS#
MA Hold from RAS#/CAS#
MD Setup to CAS#
MD Hold from CAS#
60 ns EDO Spec (ns)
40
60
20–45
10
15
0
10
0
10
0
10
66 MHz CLKs
3
5
3
1
1
1
1
1 or 2
1
1
1
4.3.5
SDRAM Paging Policy
Open page arbitration is a paging policy which leaves pages open when handing off ownership of
DRAM among masters, and places no restrictions on the number of rows which may have open
pages at any given time.
Features include:
• Pipelined arbitration allows row/bank/page operations for next cycle to occur while current
DRAM access is performed.
• Maintaining 2, or 4 banks open at once, in up to 4 rows at a time.
82443ZX Host Bridge Datasheet
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