82443ZX Datasheet, PDF (100/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
4.4
PCI Interface
The 82443ZX Host Bridge provides a PCI bus interface that is compliant with the PCI Local Bus
Specification, Revision 2.1. The implementation is optimized for high-performance data streaming
when the 82443ZX is acting as either the target or the initiator on the PCI bus. The 82443ZX
supports the conventional PCI interface referred to as PCI and AGP/PCI interface referred to as
AGP for PCI transactions and AGP for PCI transactions using the AGP enhanced protocols. AGP
cycles using the enhanced protocols are non-snoopable cycles targeted at DRAM.
4.5
AGP Interface
The 82443ZX Host Bridge provides a AGP bus interface that is compliant with the A.G.P. Interface
Specification, Revision 1.0. The 82443ZX supports AGP/PCI interface referred to as AGP for PCI
transactions and AGP for PCI transactions using the AGP enhanced protocols.
4.6
4.6.0.1
4.6.1
4.6.2
Data Integrity Support
Non-ECC (Default Mode of Operation)
After CPURST#, the 82443ZX ECC control logic is set in the default mode, no data integ-
rity or Non-ECC. This is the highest performance mode for the memory interface. Reads
from memory are not delayed for error checking and correcting and writes of less than a
QWord are performed without any overhead.
CPU Bus Integrity
The Intel^® 440ZX AGPset does not support the Pentium II processor bus integrity
mechanisms. It does not provide support for data protection via ECC, and address/
request signal protection via parity, nor does it support bus protocol error checking or
reporting.
PCI Bus Integrity
The 82443ZX implements Parity generation on the PAR pin as defined by the PCI Rev. 2.1
Specification for both Primary and Secondary PCI bus. The 82443ZX does not contain the PERR#
pin, however the 82443ZX will check and report data parity errors on either the Primary or
Secondary PCI buses. Data and address parity errors are reported on SERR#.
4-20
82443ZX Host Bridge Datasheet