82443ZX Datasheet, PDF (15/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Signal Description
Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel^® 440BX
AGPset.
Table 2-2. Host Signals Not supported by the 82443ZX
Signal
A[35:32]#
AERR#
AP[1:0]#
BINIT#
DEP[7:0]#
IERR#
INIT#
BERR#
RP#
RSP#
Function
Address
Address Parity Error
Address Parity
Bus Initialization
Data Bus ECC/Parity
Internal Error
Soft Reset
Bus Error
Request Parity
Response Parity
Signal
Not Supported By 82443ZX
Extended addressing (over 4 GB)
Parity protection on address bus
Parity protection on address bus
Checking for bus protocol violation and protocol recovery mechanism
Enhanced data bus integrity
Direct internal error observation via IERR# pin
Implemented by PIIX4E, BIST supported by external logic.
Unrecoverable error without a bus protocol violation
Parity protection on ADS# and PREQ[4:0]#
Parity protection on RS[2:0]#
2.2
DRAM Interface
Table 2-3. DRAM Interface Signals (Sheet 1 of 2)
Name
Type
Description
RASA[3:0]#
/CSA[3:0]#
RASB[3:0]#
/CSB[3:0]#
CKE[3:2]
CASA[7:0]#
/DQMA[7:0]
O
CMOS
O
CMOS
O
CMOS
Row Address Strobe (EDO): These signals are used to latch the row address
on the MAxx lines into the DRAMs. Each signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select (SDRAM): For the memory row configured with SDRAM these pins
perform the function of selecting the particular SDRAM components during the
active state.
Note that there are 2 copies of RAS# per physical memory row to improve the
loading.
CKE is used to dynamically power down inactive SDRAM rows.
Note that there are 2 copies of CS# per physical memory row to reduce the
loading.
Column Address Strobe A-side (EDO): The CASA[7:0]# signals are used to
latch the column address on the MA[13:0] lines into the DRAMs of the A half of
the memory array. These are active low signals that drive the DRAM array
directly without external buffering.
Input/Output Data Mask A-side (SDRAM): These pins control the A half of the
memory array and act as synchronized output enables during read cycles and as
a byte enables during write cycles.
82443ZX Host Bridge Datasheet
2-3