82443ZX Datasheet, PDF (102/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
Clock Control Functions Supported by 82443ZX
• Internal clock gating: this function allows the 82443ZX to gate the clock to the majority of its
logic while there is no pending events to handle.
• The Primary PCI bus includes the support of the CLKRUN#, which enables the PIIX4E to
dynamically disable the primary PCICLK and for the 82443ZX and PCI peripheral to re-
enable the clock when it is needed to perform a transaction.
• When an AGP port is not available on the system, a strapping option allows the 82443ZX to
permanently disable all clocks associated with AGP logic.
SMRAM Functions
The 82443ZX provides the normal SMRAM range mapping, in the areas below 1MB, as well as
extended SMRAM ranges that are mapped in cacheable ranges above 1MB. In addition, the
82443ZX provides the normal control mechanism to initialize, close for data accesses and lock the
SMRAM range.
Summary of ACPI Functions
The 82443ZX provides an optional decoding of pm2_control register in IO port 22h. This IO port
can be used to disable the 82443ZX arbiters for PCI and AGP initiated cycles.
Desktop vs. Mobile Power Management Functions
In general, all mobile functions of the 82443BX are not available in the 82443ZX desktop
configuration.
System Power Modes
Table 4-14 provides an overview of how the above features map into system-wide low power
modes.
Table 4-14. Low Power Mode
System Suspend 82443ZX
State
State
Description
POS Exit
PCIRST
External Clk
HCLK PCLK
HCLK PCLK
Powered-On
The 82443ZX is fully on and operating
normally.
ON
Internal clock gating as well as PCI
CLKRUN# may be enabled.
N/A
Active Active
CPU STOP_GRANT
This is transparent to the 82443ZX as
external HCLK and PCLK are
QUICK_START
ON ^{unaffected. However, host bus is idle.}
(C2)
Internal clock gating as well as PCI
CLKRUN# may be enabled
N/A
Active Active
Suspend -to-Disk
(STD) or Powered-
Off
OFF
Entire system is powered OFF except for
PIIX4E resume and RTC wells. Upon
resume, the 82443ZX resets its entire
state.
N/A
X
X
4-22
82443ZX Host Bridge Datasheet