82443ZX Datasheet, PDF (98/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
Table 4-11. MA Muxing vs. DRAM Address Split
Option 1
8 MB
Option 2
16 MB
Option 4
64 MB
Split
12x8*
11x9
10x10
12x8
12x9*
13x8*
11x10
12x9
13x8
14x9*
13x10
12x11
Row/
Col
SDRAM
A11
BA1
BA0
A10/
AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Row
11 12 14 13 22 21 20 19 18 17 16 15
Col
11 AP
10 9 8 7 6 5 4 3
Row
12 14 13 22 21 20 19 18 17 16 15
Col
11 10 9 8 7 6 5 4 3
Row
14 13 22 21 20 19 18 17 16 15
Col
12 11 10 9 8 7 6 5 4 3
Row
11 12 14 13 22 21 20 19 18 17 16 15
Col
10 9 8 7 6 5 4 3
Row
12 23 14 13 22 21 20 19 18 17 16 15
Col
12 AP
11 10 9 8 7 6 5 4 3
Row
12 11 23 14 13 22 21 20 19 18 17 16 15
Col
12 11 AP
10 9 8 7 6 5 4 3
Row
23 14 13 22 21 20 19 18 17 16 15
Col
12 11 10 9 8 7 6 5 4 3
Row
12 23 14 13 22 21 20 19 18 17 16 15
Col
11 10 9 8 7 6 5 4 3
Row
11 12 23 14 13 22 21 20 19 18 17 16 15
Col
10 9 8 7 6 5 4 3
Row
25
13 12 23 14 24 22 21 20 19 18 17 16 15
Col
13 12 AP
11 10 9 8 7 6 5 4 3
Row
13 25 23 14 24 22 21 20 19 18 17 16 15
Col
12 11 10 9 8 7 6 5 4 3
Row
25 23 14 24 22 21 20 19 18 17 16 15
Col
13 12 11 10 9 8 7 6 5 4 3
NOTE:
1. * Indicates SDRAM organization
4.3.3
SDRAMC Register Programming
Several timing parameters are programmable when using SDRAM in a Intel^® 440ZX AGPset
system. The following table summarizes the programmable parameters.
Table 4-12. Programmable SDRAM Timing Parameters
Parameter
SDRAMC Bit
CAS# Latency
RAS# to CAS# Delay
RAS# Precharge
Leadoff CS# assertion
CL
SRCD
SRP
LCT
Values (DCLKs)
2,3
2,3
2,3
3,4
The 82443ZX can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS#
Precharge. Two additional bits are provided for controlling CS# assertion. The first is the Leadoff
Timing bits which effectively control when the command lines (SRAS#, SCAS# and WE#) are
4-18
82443ZX Host Bridge Datasheet