82443ZX Datasheet, PDF (16/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Signal Description
Table 2-3. DRAM Interface Signals (Sheet 2 of 2)
Name
GCKE/CKE1
SRAS[A]#
CKE0/FENA
SCAS[A]#
MAA[13:0]
STRAP5
STRAP4
STRAP3
STRAP2
STRAP1
STRAP0
WEA#
MD [63:0]
Type
O
CMOS
O
CMOS
O
CMOS
O
CMOS
Description
Global CKE (SDRAM): Global CKE is normally used in an 82443BX 4 DIMM
configuration requiring power down mode for the SDRAM. External logic must be
used to implement this function in an 82443BX. This function is not supportrd in
an 82443ZX.
SDRAM Clock Enable (CKE1): In mobile mode, SDRAM Clock Enable is used
to signal a self-refresh or power-down command to an SDRAM array when
entering system suspend. CKE is also used to dynamically power down inactive
SDRAM rows. The combination of SDRAMPWR (SDRAM register) and
MMCONFIG (DRAMC register) determine the functioning of the CKE signals.
Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRAM Control Register
(Device 0)” on page 3-19) for more details.
SDRAM Row Address Strobe (SDRAM): The SRAS[A]# signal is a copy of the
same logical SRASx signal (for loading purposes) used to generate SDRAM
command encoded on SRASx/SCASx/WE signals.
SDRAM Clock Enable 0 (CKE0). In mobile mode, CKE0 SDRAM Clock Enable
is used to signal a self-refresh or power-down command to an SDRAM array
when entering system suspend. CKE is also used to dynamically power down
inactive SDRAM rows.
FET Enable (FENA): In a 4 DIMM configuration. FENA is used to select the
proper MD path through the FET switches (refer to Section 4.3, “DRAM Interface”
on page 4-14 for more details). This function is not supported in the 82443ZX.
SDRAM Column Address Strobe (SDRAM): The SCAS[A]# signal is a copy of
the same logical SCASx signal (for loading purposes) used to generate SDRAM
command encoded on SRASx/SCASx/WE signals.
O
CMOS
Memory Address(EDO/SDRAM): MAA[13:0] are used to provide the row and
column address to DRAM. Each MAA[13:0] line has a programmable buffer
strength to optimize for different signal loading conditions.
STRAP[5:0] are described in Table 2-10, Strapping Options.
O
CMOS
I/O
CMOS
Write Enable Signal (EDO/SDRAM): WE# is asserted during writes to DRAM.
The WE# lines have a programmable buffer strength to optimize for different
signal loading conditions.
Memory Data (EDO/SDRAM): These signals are used to interface to the DRAM
data bus.
2-4
82443ZX Host Bridge Datasheet