82443ZX Datasheet, PDF (106/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
The SMI handler can set the CLS bit to enable data accesses to aliased memory space, while code
fetches access the SMRAM space.
Extended SMRAM (E_SMRAM)
This feature in the 82443ZX extend the SMRAM space up to 1 MB and provide write-back
cacheability.
The TSEG size is 128 KBs, 256 KBs, 512 KBs or 1 MB, as defined by TSEG_SZ[1:0] of the
SMRAMC register.
The CPU can access these memory ranges by one of the following mechanisms:
• The processor can access SMRAM while in the SMM mode. A processor access to while not
in SMM and with while the D_OPN bit is reset will be forwarded to PCI bus and a status bit is
set in the SMRAMC register.
• The processor can access SMRAM while the D_OPN bit is set.
4-26
82443ZX Host Bridge Datasheet