82443ZX Datasheet, PDF (41/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Register Description
Bit
Description
ECC - EDO Static Drive Mode
This bit should be set to “0”. The 82443ZX does not support ECC.
17
IDSEL_REDIRECT. This is a programmable option to make the 82443ZX compatible with 430TX
base design. For CPU initiated configuration cycles to PCI, Device 1 which are targeted to the
82443ZX’s host to AGP bridge:
0 = When set to ‘0’ (default), IDSEL1 (or AD12) is allocated to this bridge. The external AD12 is
never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus
device that its IDSEL input is connected to IDSEL7 (AD18).
16
1 = When set to ‘1’, IDSEL7 (or AD18) is allocated to this bridge. Since it is internal in the
82443ZX, the external AD18 is never activated. CPU initiated configuration cycles to BUS0,
DEVICE7 are targeted a PCI bus device that its IDSEL input is connected to IDSEL1 (AD12).
In some 430TX based systems, this is connected to PIIX4E.
Note that CPU initiated configuration cycles to other PCI buses or other devices are normally
mapped and are not affected.
WSC# Handshake Disable
15
This bit should be set to “1” for single processor use. The 82443ZX does not support the I/O APIC
or dual processors.
Intel Reserved.
14
13:12
Host/DRAM Frequency.
These bits are used to determine the host and DRAM frequency. Bit 13 is set by an external
strapping option at reset. These bits are also used to select the required refresh rate. These bits
apply to both SDRAM and EDO, with the exception that setting “00” for 100MHz is illegal for an
EDO system.
00 = 100MHz
01 = Reserved
10 = 66MHz
11 = Reserved
AGP to PCI Access Enable. When PHLDA# is active or there is an outstanding passive release
transaction pending: 1) this bit is set to 1 and the 82443ZX allows AGP to PCI traffic, or 2) this bit
is set to 0 (default) and the 82443ZX blocks AGP to PCI traffic. The AGP to PCI traffic must not
11
target the ISA bus.
1 = Enable
0 =Disable
PCI Agent to Aperture Access Disable. This bit is used to prevent access to the aperture from
the PCI side.
1 = Disable
10
0 = Enable (default). If this bit is “0” (default) and bit 9 = 1, accesses to the aperture are enabled
for the PCI side.
Note: This bit is don’t care if bit 9 of this register = 0.
Aperture Access Global Enable. This bit is used to prevent access to the aperture from any port
(CPU, PCI or AGP) before aperture range is established by the configuration software and
appropriate translation table in the main DRAM has been initialized. Default is “0”. It must be set
9
after system is fully configured for aperture accesses.
1 = Enable. Note that this bit globally controls accesses to the aperture. Once enabled, bit 10
provides the next level of control for accesses originated from the PCI side.
0 = Disable
82443ZX Host Bridge Datasheet
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